Three-dimensional semiconductor device and method of fabricating same

Patent metadata

Field	Value
Publication number	US-10825868-B2
Application number	US-201816234381-A
Country	US
Kind code	B2
Filing date	Dec 27, 2018
Priority date	Dec 29, 2017
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.

First claim

What is claimed is:

1. A method of manufacturing a three-dimensional semiconductor device, the method comprising:
providing a vertical stack of alternating layers of a first layer type and a second layer type;
providing a first trench and a second trench adjacent to the vertical stack, the first trench and the second trench defining a fin;
recessing the first layer type to form recesses extending into the fin;
providing a first electrode in individual ones of the recesses;
providing a second electrode in the first trench and the second trench; and
providing a lateral stack comprising a memory element, a middle electrode, and a selector element, the lateral stack stacked in a lateral direction and extending between the first electrode in the individual ones of the recesses and the second electrode, thereby forming a memory device, wherein the memory element or the selector element is formed at least partly outside of the individual ones of the recesses.

2. The method according to claim 1 , wherein providing the first trench and the second trench comprises forming the first trench and the second trench in the vertical stack.

3. The method according to claim 1 , wherein providing the first electrode comprises:
filling the recesses with a first conductive material; and
recessing at least some of the first conductive material back into the recesses.

4. The method according to claim 3 , wherein providing the lateral stack comprises:
lining individual ones of the recesses with a selector element material forming the selector element;
filling individual ones of the recesses with a second conductive material forming the middle electrode; and
forming the memory element by providing a memory element material in the first trench and the second trench.

5. The method according to claim 1 , wherein providing the lateral stack comprises:
forming the memory element by filling the recesses with a memory element material; and
recessing at least some of the memory element material back into the recesses.

6. The method according to claim 1 , wherein providing the lateral stack comprises:
forming the middle electrode by filling the recesses with a second conductive material; and
recessing at least some of the second conductive material back into the recesses.

7. The method according to claim 1 , wherein providing the lateral stack comprises:
forming the selector element by providing a selector element material in the first trench and the second trench.

8. The method according to claim 1 , wherein the first layer type comprises a first electrical insulating material and the second layer type comprises a second electrical insulating material.

9. The method according to claim 1 , further comprising:
providing the vertical stack with a staircase connection structure configured to individually connect the first electrode in individual ones of the recesses of the fin.

10. The method according to claim 9 , further comprising forming a second electrode material into a plurality of contact structures configured to connect the fin with a neighboring fin.

11. The method according to claim 10 , wherein the contact structures are shaped as separated lines or dots.

12. The method according to claim 10 , further comprising removing a selector element material between the plurality of contact structures.

13. The method according to claim 10 , further comprising removing a second conductive material between the plurality of contact structures.

14. The method according to claim 10 , further comprising:
connecting, via the staircase connection structure, the first electrode in individual ones of the recesses to a respective word line; and
connecting individual ones of the plurality of contact structures to a respective bit line.

15. A semiconductor device comprising:
a vertical stack of alternating layers of a first layer type and a second layer type;
a fin defined by a first trench and a second trench adjacent the vertical stack;
recesses extending laterally from the first trench and the second trench, respectively, into the fin;
a first electrode in individual ones of the recesses;
a second electrode in the first trench and the second trench; and
a lateral stack comprising a memory element, a middle electrode, and a selector element, the lateral stack being arranged to extend between the first electrode in individual ones of the recesses and the second electrode, thereby forming a memory device, wherein the memory element or the selector element is formed at least partly outside of the individual ones of the recesses.

16. The semiconductor device according to claim 15 , wherein the vertical stack comprises a staircase connection structure configured to individually connect the first electrode in individual ones of the recesses of the fin.

17. The semiconductor device according to claim 16 , wherein the second electrode material provides a plurality of contact structures configured to connect the fin with a neighboring fin.

18. The semiconductor device according to claim 17 , wherein, via the staircase connection structure, the first electrode in individual ones of the recesses is configured to connect to a respective word line, and wherein the plurality of contact structures is configured to connect to a respective bit line.

19. The semiconductor device according to claim 15 , wherein the memory element and middle electrode are disposed in individual ones of the recesses, and the selector element is disposed in the first and second trenches.

20. The semiconductor device according to claim 15 , wherein the selector element and middle electrode are disposed in individual ones of the recesses, and the memory element is disposed in the first and second trenches.

Assignees

• Imec Vzw

Inventors

• Delhougne Romain
• Crotti Davide Francesco
• Kar Gouri Sankar
• Di Piazza Luca
• Goux Ludovic

Classifications

• H10B63/84 Primary

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H01L45/1683

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L27/11597

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic