Low latency memory erase suspend operation

Patent metadata

Field	Value
Publication number	US-10825529-B2
Application number	US-201414455749-A
Country	US
Kind code	B2
Filing date	Aug 8, 2014
Priority date	Aug 8, 2014
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array includes a plurality of blocks of memory cells, each block including a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells.

First claim

What is claimed is:

1. A circuit comprising:
a nonvolatile memory array comprising a plurality of blocks of memory cells, each block comprising a plurality of sectors of memory cells;
peripheral circuitry coupled to word lines and bit lines in the array, including an address decoder, a page buffer, and biasing arrangement supply voltage sources; and
control logic coupled to the peripheral circuitry, the control logic configured to respond to an erase command identifying a block of the plurality of the blocks by:
executing an erase operation for the sectors in the plurality of sectors, the erase operation including for a current sector an erase and erase verify sequence followed by a soft program sequence, the erase and erase verify sequence configured to:
apply one or more erase pulses to the current sector, and
identify one or more over-erased cells in the current sector,
wherein, in response to an erase suspend command received during the erase operation, after identifying one or more over-erased cells and before the soft program sequence for the current sector, a weak program correction pulse is applied to the identified one or more over-erased cells, the weak program correction pulse increasing the threshold voltage of the identified one or more over-erased cells;
wherein said erase and erase verify sequence is configured to identify one or more over-erased cells in the current sector by iteratively applying an over-erase threshold voltage with incremental change until only said one or more over-erased cells pass.

2. A circuit comprising:
a nonvolatile memory array;
peripheral circuitry coupled to word lines and bit lines in the array, including an address decoder, a page buffer, and biasing arrangement supply voltage sources; and
control logic coupled to the peripheral circuitry, the control logic being configured to:
respond to an erase command identifying a block of memory cells in the array, by executing an erase operation including an erase sequence applying an erase bias that reduces threshold voltages of memory cells in the block, and an erase verify sequence that determines whether the memory cells in the block have threshold voltages below a first erase verify level, and that identifies one or more memory cells in the block that have threshold voltage below a second erase verify level, lower than the first erase verify level; and
respond to an erase suspend command received after the erase verify sequence identifies one or more memory cells in the block that have threshold voltage below the second erase verify level by executing an erase suspend operation suspending the erase operation, including selectively applying a weak program bias arrangement to the identified one or more memory cells, the weak program bias arrangement increasing the threshold voltage of the identified one or more memory cells, and allowing the control logic to execute another operation on the memory array;
wherein the weak program bias arrangement is applied only to the identified one or more memory cells.

Assignees

• Macronix Int Co Ltd

Inventors

• Hsu Wen-Ming
• Kuo Nai-Ping
• Hung Chun-Hsiung

Classifications

• G11C16/3409

  Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title