Approach for logic signal grouping and RTL generation using XML

Patent metadata

Field	Value
Publication number	US-10824783-B2
Application number	US-201514675403-A
Country	US
Kind code	B2
Filing date	Mar 31, 2015
Priority date	Mar 31, 2015
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

Systems and methods for generating an RTL description based on logical signal groupings are described. Logical interfaces are declared in a compressed form, and logical signal grouping is defined in a markup document. The definitions from the markup document are used by expansion scripts to populate RTL modules and encapsulate block connectivity and functionality. Multiple interfaces can be created instantly, and interface definitions for common interfaces may be easily re-defined. Default values may be assigned to module outputs for testing purposes, allowing for multi-module simulations where certain modules are shelled-out.

First claim

What is claimed is:

1. A method, performed by a processor, for generating a register transfer level (RTL) description using logical signal grouping, the method comprising:
generating a plurality of logical interface definitions, wherein the plurality of logical interface definitions define signals from an output module to an input module and comprise an interface rule;
defining a data structure in a structured document, wherein the data structure comprises a first set of logical interfaces, and wherein the structured document is used to define the logical signal grouping for each logical interface of the first set of logical interfaces;
executing an expansion script to generate a first RTL description using the structured document, wherein the first RTL description comprises a plurality of RTL modules that communicate using the plurality of logical interface definitions, wherein the first RTL description is populated based on the plurality of logical interface definitions, the interface rule, the logical signal grouping defined in the structured document, and the data structure, and wherein the generated first RTL description facilitates reuse of physical components of an integrated circuit (IC) without implementing physical changes to the physical components to accommodate different placements, routings, and orientations;
modifying a first logical interface from the first set of logical interfaces of the data structure to automatically generate a second RTL description based on the expansion script using the data structure defined in the structured document;
assigning a default value to a first output of a first RTL module of the plurality of RTL modules and testing a second RTL module of the plurality of RTL modules using the first output, wherein the assigning the default value comprises assigning a default value to a logical interface, related to the first RTL module, in the structured document; and
generating objects and sequence items based on the logical signal grouping, wherein the generated objects and the generated sequence items are to be used for error testing and use of drivers and monitors.

2. The method of claim 1 , wherein the first set of logical interfaces are bi-directional.

3. The method of claim 1 , further comprising assigning a default value to a control signal of the first set of logical interfaces.

4. The method of claim 1 , further comprising automatically generating a documentation file comprising a direction, a size, and a description of the signals.

5. The method of claim 1 , wherein the structured document is an XML, file.

6. The method of claim 1 , wherein the first RTL description comprises structured HDL code.

7. The method of claim 1 , wherein the first RTL description comprises an automatically generated struct comprising a plurality of signals.

8. The method of claim 1 , further comprising automatically generating an assertion based on the structured document for testing a condition of the first RTL module of the plurality of RTL modules.

9. A computer program product tangibly embodied in a computer-readable storage device and comprising instructions, that when executed by a processor, perform a method for generating a register transfer level (RTL) description using logical signal grouping, the method comprising:
generating a plurality of logical interface definitions, wherein the plurality of logical interface definitions define signals from an output module to an input module and comprise an interface rule;
defining a data structure in a structured document, wherein the data structure comprises a first set of logical interfaces, and wherein the structured document is used to define the logical signal grouping for each logical interface of the first set of logical interfaces;
executing an expansion script to generate a first RTL description using the structured document, wherein the first RTL description comprises a plurality of RTL modules that communicate using the plurality of logical interface definitions, wherein the first RTL description is populated based on the plurality of logical interface definitions, the interface rule, the logical signal grouping defined in the structured document, and the data structure, and wherein the generated first RTL description facilitates reuse of physical components of an integrated circuit (IC) without implementing physical changes to the physical components to accommodate different placements, routings, and orientations;
modifying a first logical interface from the first set of logical interfaces of the data structure to automatically generate a second RTL description based on the expansion script using the data structure defined in the structured document;
assigning a default value to a first output of a first RTL module of the plurality of RTL modules and testing a second RTL module of the plurality of RTL modules using the first output, wherein the assigning the default value comprises assigning a default value to a logical interface, related to the first RTL module, in the structured document; and
generating objects and sequence items based on the logical signal grouping, wherein the generated objects and the generated sequence items are to be used for error testing and use of drivers and monitors.

10. The method of claim 9 , wherein the first set of logical interfaces are bi-directional.

11. The method of claim 9 , further comprising assigning a default value to a control signal of the first set of logical interfaces.

12. The method of claim 9 , further comprising automatically generating a documentation file comprising a direction, a size, and a description of the signals.

13. The method of claim 9 , wherein the structured document is an XML file.

14. The method of claim 9 , wherein the first RTL description comprises structured HDL code.

15. The method of claim 9 , wherein the first RTL description comprises an automatically generated struct comprising a plurality of signals.

16. The method of claim 9 , further comprising automatically generating an assertion based on the structured document for testing a condition of the first RTL module of the plurality of RTL modules.

17. A system comprising:
at least one processor; and
at least one computer-readable storage device comprising instructions, that when executed by the at least one processor, cause performance of a method for generating a register transfer level (RTL) description using logical signal grouping, the method comprising:
generating a plurality of logical interface definitions, wherein the plurality of logical interface definitions define signals from an output module to an input module and comprise an interface rule;
defining a data structure in a structured document, wherein the data structure comprises a first set of logical interfaces, and wherein the structured document is used to define the logical signal grouping for each logical interface of the first set of logical interfaces;
executing an expansion script to generate a first RTL description using the structured document, wherein the first RTL description comprises a plurality of RTL modules that communicate using the plurality of logical interface definitions, wherein the first RTL description is populated based on the plurality of logical interface definitions, the interface rule, the logical signal grouping defined in the structured document, and the data structure, and wherein the generated first RTL description facilitates reuse of physical components of an integrated circuit (IC) without implementing physical changes to the physical components to accommodate differ

Assignees

• Xpliant
• Marvell Asia Pte Ltd

Inventors

• Theivendran Premshanth
• Wang Weihuang
• Hutchison Guy
• Schmidt Gerald

Classifications

• G06F30/30 Primary

  Circuit design · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/3308

  using simulation · CPC title