Apparatuses and methods involving self-testing voltage regulation circuits

Patent metadata

Field	Value
Publication number	US-10823787-B2
Application number	US-201816009836-A
Country	US
Kind code	B2
Filing date	Jun 15, 2018
Priority date	Jun 15, 2018
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

An apparatus embodiment includes a voltage regulator circuit that provides a regulated voltage supply signal, logic state circuitry, test control circuitry, and a supply-signal monitoring circuit. The logic state circuitry includes logic modules that are reconfigured between application controlled self-test modes in which data is shifted through the logic module and while being powered from the regulated voltage supply signal. The test control circuitry operates the controlled self-test mode by causing a predetermined set of the data to shift through the logic modules and that causes the logic state circuitry to load the voltage regulator circuit by stressing the voltage regulator circuit. The supply-signal monitoring circuit monitors a quality parameter of the regulated voltage supply signal and provides an indication of characteristics of the regulated voltage supply signal which bear on a likelihood that the voltage regulator circuit is associated with defective circuitry.

First claim

What is claimed is:

1. An apparatus comprising:
a voltage regulator circuit configured and arranged to provide a regulated voltage supply signal as a voltage supply source;
logic state circuitry including logic modules configured and arranged to be reconfigured between an application mode and a controlled self-test mode in which data is shifted through the logic modules in response to a clock signal while being powered from the regulated voltage supply signal;
test control circuitry configured and arranged to operate the controlled self-test mode by causing a predetermined set of the data to shift through the logic modules using a scan mode that causes the logic state circuitry to load the voltage regulator circuit by stressing the voltage regulator circuit, wherein the predetermined set of the data causes each of the logic modules of the logic state circuitry to be exercised for the controlled self-test mode; and
a supply-signal monitoring circuit configured and arranged to monitor at least one quality parameter of the regulated voltage supply signal and, in response provide an indication of characteristics of the regulated voltage supply signal which bear on a likelihood that continued operation of the voltage regulator circuit is associated with defective circuitry that is utilized in providing the regulated voltage supply signal to the logic state circuitry.

2. The apparatus of claim 1 , wherein the test control circuitry and the supply-signal monitoring circuit are cooperatively configured and arranged to maximize stress on the voltage regulator circuit during the controlled self-test mode, while using the supply-signal monitoring circuit to test the voltage regulator circuit.

3. The apparatus of claim 1 , wherein the logic modules include multiplexers and flip-flops configurable for operating as scan-chains in the controlled self-test mode, and wherein the test control circuitry is further configured and arranged to cause the logic state circuitry to load the voltage regulator circuit by shifting the data in a circular manner that includes feedback, wherein the data is shifted through and out of the scan-chains and back into an input of the scan-chains so that the data is restored in the logic state circuitry at commencement of the data being shifted during the controlled self-test mode.

4. The apparatus of claim 1 , wherein the logic modules are scan-chains configurable for operating in the controlled self-test mode, and wherein the test control circuitry is further configured and arranged to cause the logic state circuitry to extremely load the voltage regulator circuit by shifting the data in a circular manner that includes feedback to so that a number n of data shifts through the logic state circuitry by n shift clock cycles, previous contents of the logic state circuitry are restored.

5. The apparatus of claim 1 , wherein the test control circuitry is further configured and arranged to cause the logic state circuitry to load the voltage regulator circuit by causing a predefined data pattern, and which causes the logic state circuitry to extremely load the voltage regulator circuit, to be shifted through the logic state circuitry.

6. The apparatus of claim 1 , wherein the voltage regulator circuit includes a low-dropout voltage regulator (LDO).

7. The apparatus of claim 1 , wherein the test control circuitry is further configured and arranged to provide the clock signal.

8. The apparatus of claim 1 , wherein the test control circuitry is further configured and arranged to operate independent of the voltage regulator circuit and of the logic modules of the logic state circuitry including operating when the voltage regulator circuit fails.

9. The apparatus of claim 1 , wherein the test control circuitry is further configured and arranged to monitor a level of integrity of the logic state circuitry including the logic modules.

10. The apparatus of claim 1 , wherein the supply-signal monitoring circuit includes an analog-to-digital converter configured and arranged to provide an indication in digital form to measure the at least one quality parameter of the regulated voltage supply signal.

11. The apparatus of claim 1 , wherein the supply-signal monitoring circuit includes a noise-level sensor.

12. The apparatus of claim 1 , wherein the supply-signal monitoring circuit includes a voltage-level detection circuit.

13. The apparatus of claim 1 , wherein the supply-signal monitoring circuit is configured and arranged to test the voltage regulator circuit by monitoring power-related characteristics.

14. The apparatus of claim 1 , wherein the logic modules and the test control circuitry are configured and arranged to operate during the application mode, and wherein the test control circuitry is further configured and arranged to control the supply-signal monitoring circuit for indicating whether the supply-signal monitoring circuit operates in the application mode or the controlled self-test mode.

15. The apparatus of claim 1 , further including another voltage-source supply signal which supplies operating power to the test control circuitry during the controlled self-test mode and which continues to supply the operating power in the event that the voltage regulator circuit fails.

16. The apparatus of claim 1 wherein the defective circuitry includes circuitry of the voltage regulator circuit.

17. The apparatus of claim 1 wherein the defective circuitry includes a voltage supply rail coupled to the voltage regulator circuit, wherein the logic state circuitry is powered from the regulated voltage supply signal received via the voltage supply rail.

18. A method including
providing a regulated voltage supply signal as a voltage supply source by a voltage regulator circuit of an apparatus;
reconfiguring logic state circuitry including logic modules of the apparatus between an application mode and a controlled self-test mode in which data is shifted through the logic modules in response to a clock signal while being powered from the regulated voltage supply signal;
causing, during the controlled self-test mode, a predetermined set of the data to shift through the logic modules using a scan mode that causes the logic state circuitry to load the voltage regulator circuit by stressing the voltage regulator circuit, wherein the predetermined set of the data causes each of the logic modules of the logic state circuitry to be exercised for the controlled self-test mode; and
monitoring at least one quality parameter of the regulated voltage supply signal and, in response, providing an indication of characteristics of the regulated voltage supply signal which bear on a likelihood that continued operation of the voltage regulator circuit is associated with defective circuitry that is utilized in providing the regulated voltage supply signal to the logic state circuitry.

19. The method of claim 18 , further including monitoring at least two of the following power-related characteristics: noise, signal overshoot, signal undershoot, voltage signal settling time, and static voltage accuracy at minimum and/or maximum load current.

20. The method of claim 18 , further including storing test results collected during the controlled self-test mode and comparing the test results against other test results.

21. The method of claim 18 , further including comparing results from the controlled self-test mode with threshold levels corresponding to the likelihood that continued operation of the voltage regulator circuit is associated

Assignees

• Nxp Bv

Inventors

• Schat Jan-Peter

Classifications

• G05F1/625

  wherein it is irrelevant whether the variable actually regulated is AC or DC · CPC title

• G01R31/3187 Primary

  Built-in tests · CPC title

• G01R31/318555

  Control logic · CPC title

• G01R1/28

  Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title