System of referenceless clock and data recovery and frequency detector thereof

Patent metadata

Field	Value
Publication number	US-10819348-B2
Application number	US-201916403361-A
Country	US
Kind code	B2
Filing date	May 3, 2019
Priority date	Nov 21, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A system of referenceless clock and data recovery and a frequency detector thereof has been provided. The output clock of the system initially works at the lowest frequency, the frequency of the output clock is monotonically increased in accordance with the control of the frequency detector, thereby gradually approximating a target value. The edge extraction circuit receives the data signal and the clock signal, identifies the transition edges of the signals and generates a data transition signal and a clock transition signal representing the transition edges of the data signal and the transition edges of the clock signal respectively. The edge detector then determines the data period of the data signal and the clock period of the clock signal. When the data period is smaller than half of the clock period, the edge detector generates a frequency-up signal and the frequency of the output clock is increased.

First claim

What is claimed is:

1. A frequency detector suitable for a clock and data recovery system to monotonically increase a frequency of a clock signal outputted by the clock and data recovery system, the frequency detector comprising:
an extraction circuit receiving a data signal and generating a data transition signal by distinguishing a plurality of data transition edges of the data signal, and the extraction circuit receiving the clock signal and generating a clock transition signal by distinguishing a plurality of clock transition edges of the clock signal; and
a determination circuit connected to the extraction circuit, and receiving the data transition signal and the clock transition signal, the determination circuit respectively determining a data signal period of the data signal and a clock signal period of the clock signal based on the data transition signal and the clock transition signal, and the determination circuit determines the period difference by comparing the relative position between the data transition signal and the clock transition signal;
wherein when the data signal period is lower than a half of the clock signal period, the determination circuit generates a frequency-up conversion signal such that the frequency of the clock signal is increased by the clock and data recovery system according to the frequency-up conversion signal.

2. The frequency detector according to claim 1 , wherein the determination circuit defines two of the plurality of data transition edges adjacent to each other as data transition intervals and two of the plurality of clock transition edges adjacent to each other as clock transition intervals based on the data transition signal and the clock transition signal, and when any of the clock transition intervals encompasses the data transition intervals on a time axis, the determination circuit generates the frequency-up conversion signal.

3. The frequency detector according to claim 2 , wherein the plurality of data transition edge adjacent is respectively a data rising edge or a data falling edge, whereas the plurality of clock transition edges adjacent are respectively a clock rising edge or a clock falling edge, and when any one of the clock rising edges or the clock falling edges leads the data rising edges or the data falling edges and the clock falling edge or the clock rising edge adjacent to the clock rising edges or the clock falling edges lags the data falling edge or the data rising edge adjacent to the data rising edges or the data falling edges, the determination circuit generates the frequency-up conversion signal.

4. The frequency detector according to claim 3 , the determination circuit generates the frequency-up conversion signal when satisfying one of the following conditions or combination thereof as below:
a first condition: the clock rising edge leads the data rising edge, and the clock falling edge adjacent to the clock rising edge lags the data falling edge adjacent to the data rising edge;
a second condition: the clock falling edge leads the data rising edge, and the clock rising edge adjacent to the clock falling edge lags the data falling edge adjacent to the data rising edge;
a third condition: the clock rising edge leads the data falling edge, and the clock falling edge adjacent to the clock rising edge lags the data rising edge adjacent to the data falling edge; and
a fourth condition: the clock falling edge leads the data falling edge, and the clock rising edge adjacent to the clock falling edge lags the data rising edge adjacent to the data falling edge.

5. The frequency detector according to claim 1 , wherein the extraction circuit further comprises:
a first D flip-flop comprising a first data input terminal, a first clock input terminal, a first temporary data output terminal and a first reset gate, the first data input terminal connected to a high voltage terminal, the first clock input terminal receiving the data signal;
a first negative-edge-triggered D flip-flop comprising a first negative-edge-triggered D flip-flop data input terminal, a first negative-edge-triggered D flip-flop clock input terminal, a first negative-edge-triggered D flip-flop data output terminal and a first negative-edge-triggered D flip-flop reset gate, the first negative-edge-triggered D flip-flop data input terminal connected to the first temporary data output terminal, the first negative-edge-triggered D flip-flop clock input terminal receiving the data signal;
a second D flip-flop comprising a second data input terminal, a second clock input terminal, a second temporary data output terminal and a second reset gate, the second data input terminal connected to the high voltage terminal, the second clock input terminal receiving the clock signal, the first reset gate connected to the second reset gate;
a second negative-edge-triggered D flip-flop comprising a second negative-edge-triggered D flip-flop data input terminal, a second negative-edge-triggered D flip-flop clock input terminal, a second negative-edge-triggered D flip-flop data output terminal and a second negative-edge-triggered D flip-flop reset gate, the second negative-edge-triggered D flip-flop data input terminal connected to the second temporary data output terminal, the second negative-edge-triggered D flip-flop clock input terminal receiving the clock signal, the second negative-edge-triggered D flip-flop reset gate connected to the first negative-edge-triggered D flip-flop reset gate; and
a first AND gate provided with a first AND gate first input terminal, a first AND gate second input terminal and a first AND gate output terminal, the first AND gate first input terminal connected to the first negative-edge-triggered D flip-flop data output terminal, the first AND gate second input terminal connected to the second negative-edge-triggered D flip-flop data output terminal, the first AND gate output terminal connected to the first reset gate, the second reset gate, the first negative-edge-triggered D flip-flop reset gate and the second negative-edge-triggered D flip-flop reset gate.

6. The frequency detector according to claim 5 , wherein the determination circuit further comprises:
a third D flip-flop comprising a third data input terminal, a third clock input terminal, a third temporary data output terminal and a third reset gate, the third data input terminal connected between the second temporary data output terminal and the second negative-edge-triggered D flip-flop data input terminal, the third clock input terminal connected between the first temporary data output terminal and the first negative-edge-triggered D flip-flop data input terminal;
a fourth D flip-flop comprising a fourth data input terminal, a fourth clock input terminal, a fourth temporary data output terminal and a fourth reset gate, the fourth data input terminal connected between the first negative-edge-triggered D flip-flop data output terminal and the first AND gate first input terminal, the fourth clock input terminal connected between the second negative-edge-triggered D flip-flop data output terminal and the first AND gate second input terminal and the third reset gate connected to the fourth reset gate; and
a second AND gate provided with a second AND gate first input terminal, a second AND gate second input terminal and a second AND gate output terminal, the second AND gate second input terminal connected to the third temporary data output terminal, the second AND gate first input terminal connected to the fourth temporary data output terminal, and the second AND gate output terminal outputting the frequency-up conversion signal.

7. A referenceless clock and data recovery system comprising:
a voltage-controlled oscillator generating a clock signal;
an extraction circuit receiving a

Assignees

• Univ National Chiao Tung

Inventors

• Chen Wei-Zen

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title