Multiplying delay locked loops with compensation for realignment error

Patent metadata

Field	Value
Publication number	US-10340902-B1
Application number	US-201815966368-A
Country	US
Kind code	B1
Filing date	Apr 30, 2018
Priority date	Apr 30, 2018
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.

First claim

What is claimed is:

1. A multiplying delay locked loop (MDLL) with compensation for realignment error, the MDLL comprising:
a multiplexed oscillator configured to generate an oscillator signal;
a control circuit configured to selectively inject a reference clock signal into the multiplexed oscillator to provide phase realignment; and
an integrate and subtract circuit configured to compensate for a realignment error of the multiplexed oscillator based on determining a difference between a first integral of the oscillator signal and a second integral of the oscillator signal.

2. The MDLL of claim 1 , wherein the integrate and subtract circuit is configured to determine the first integral when the control circuit injects the reference clock signal into the multiplexed oscillator, and to determine the second integral when the control circuit does not inject the reference clock signal into the multiplexed oscillator.

3. The MDLL of claim 1 , wherein the integrate and subtract circuit comprises a switched resistor-capacitor (RC) integrator.

4. The MDLL of claim 3 , wherein the switched RC integrator comprises a differential amplifier configured to generate a differential signal representing the difference between the first integral and the second integral, wherein the switched RC integrator comprises an input offset compensation circuit configured to compensate for an input offset of the differential amplifier.

5. The MDLL of claim 1 , wherein the multiplexed oscillator comprises a controllable delay element, wherein the integrate and subtract circuit is configured to control a delay of the controllable delay element.

6. The MDLL of claim 1 , wherein the multiplexed oscillator comprises a controllable delay element, wherein the MDLL further comprises a phase-frequency detector and charge pump configured to control a delay of the controllable delay element based on comparing timing of the multiplexed oscillator to timing of the reference clock signal.

7. The MDLL of claim 6 , wherein the integrate and subtract circuit is configured to calibrate the phase-frequency detector and charge pump based on the difference.

8. The MDLL of claim 7 , further comprising a loop filter coupled to an output of the phase-frequency detector and charge pump, wherein the integrate and subtract circuit is operable to calibrate an amount of leakage current to the loop filter.

9. The MDLL of claim 7 , wherein the phase-frequency detector and charge pump comprises a first detection element and a second detection element configured to compare the timing of the multiplexed oscillator to the timing of the reference clock signal, wherein the integrate and subtract circuit is operable to calibrate a delay in resetting the first detection element relative to a delay in resetting the second detection element.

10. An electronic system comprising:
a multiplying delay locked loop (MDLL) configured to generate an output clock signal based on timing of a reference clock signal, wherein the MDLL comprises:
a multiplexed oscillator configured to generate an oscillator signal, wherein the multiplexed oscillator includes a multiplexer configured to receive the reference clock signal and the oscillator signal; and
an integrate and subtract circuit configured to compensate for a realignment error of the multiplexed oscillator based on a difference between a first integral of the oscillator signal and a second integral of the oscillator signal; and

a downstream circuit having timing controlled by the output clock signal of the MDLL.

11. The electronic system of claim 10 , wherein the integrate and subtract circuit is configured to determine the first integral when the multiplexer selects the reference clock signal, and to determine the second integral when the multiplexer selects the oscillator signal.

12. The electronic system of claim 10 , wherein the integrate and subtract circuit comprises a switched RC integrator.

13. The electronic system of claim 12 , wherein the switched RC integrator comprises a differential amplifier configured to generate a differential signal representing the difference between the first integral and the second integral, wherein the switched RC integrator comprises an input offset compensation circuit configured to compensate for an input offset of the differential amplifier.

14. The electronic system of claim 10 , wherein the multiplexed oscillator comprises a controllable delay element, wherein the integrate and subtract circuit is configured to control a delay of the controllable delay element.

15. The electronic system of claim 10 , further comprising a control circuit configured to control selection of the multiplexer based on timing of the output clock signal.

16. The electronic system of claim 10 , wherein the downstream circuit comprises a frequency synthesizer, wherein the output clock signal of the MDLL is configured to control an input reference frequency to the frequency synthesizer.

17. The electronic system of claim 10 , wherein the downstream circuit comprises a data conversion circuit having timing of data conversion operations controlled by the output clock signal of the MDLL.

18. A method of compensating for realignment error in a multiplying delay locked loop (MDLL), the method comprising:
generating an oscillator signal using a multiplexed oscillator, including regularly injecting a reference clock signal into the multiplexed oscillator to thereby provide phase realignment;
determining a first integral of the oscillator signal;
determining a second integral of the oscillator signal; and
compensating for a realignment error of the multiplexed oscillator based on a difference between the first integral and the second integral.

19. The method of claim 18 , wherein determining the first integral comprises integrating the oscillator signal while the reference clock signal is being injected, and wherein determining the second integral comprises integrating the oscillator signal while the reference clock signal is not being injected.

20. The method of claim 18 , further comprising controlling an adjustable delay of the multiplexed oscillator based on the difference between the first integral and the second integral.

Assignees

• Analog Devices Global Unlimited Co

Inventors

• Fortier Justin L
• Katumba Rachel

Classifications

• H03L7/0816

  the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/16

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title