Semiconductor device and memory system

Patent metadata

Field	Value
Publication number	US-10819295-B2
Application number	US-201916557019-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Feb 19, 2019
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. The fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.

First claim

What is claimed is:

1. A semiconductor device comprising a first differential amplifier circuit,
wherein the first differential amplifier circuit includes:
a first transistor;
a second transistor of which gate and drain are connected to the first transistor;
a third transistor diode-connected through the first transistor or diode-connected without passing through the first transistor;
a fourth transistor diode-connected through the second transistor or diode-connected without passing through the second transistor;
a fifth transistor which forms a first current mirror circuit with the third transistor; and
a sixth transistor which is connected to a drain of the first transistor in parallel with the third transistor and which forms a second current mirror circuit with the fifth transistor.

2. The semiconductor device according to claim 1 , wherein
the third transistor is diode-connected through the first transistor, and
the fourth transistor is diode-connected through the second transistor.

3. The semiconductor device according to claim 2 , wherein
a gate of the first transistor is connected to a gate of the fourth transistor and the drain of the second transistor, and
the gate of the second transistor is connected to a gate of the third transistor and the drain of the first transistor.

4. The semiconductor device according to claim 1 , wherein
the third transistor is diode-connected without passing through the first transistor, and
the fourth transistor is diode-connected without passing through the second transistor.

5. The semiconductor device according to claim 4 , wherein
a gate of the first transistor is connected to a gate and a drain of the fourth transistor, and
the gate of the second transistor is connected to a gate and a drain of the third transistor.

6. The semiconductor device according to claim 1 , wherein
the first differential amplifier circuit further includes:
a seventh transistor which is connected in series to the sixth transistor and which receives a first input signal at a gate; and
an eighth transistor connected to the drain of the second transistor in parallel with the fourth transistor.

7. The semiconductor device according to claim 6 , wherein
the first differential amplifier circuit further includes
a ninth transistor which forms a differential pair with the seventh transistor, which is connected in series to the eighth transistor at a source, and which receives a reference signal at a gate.

8. The semiconductor device according to claim 6 , wherein
the first differential amplifier circuit further includes
a ninth transistor which forms a differential pair with the seventh transistor, which is connected in series to the eighth transistor at a source, and which receives a second input signal logically inverted from the first input signal at a gate.

9. The semiconductor device according to claim 7 further comprising
a potential adjustment circuit connected to a source of the sixth transistor.

10. The semiconductor device according to claim 9 , wherein
the potential adjustment circuit includes
a tenth transistor which is connected to the source of the sixth transistor in parallel with the seventh transistor and which is diode-connected through the sixth transistor.

11. The semiconductor device according to claim 9 further comprising
a second potential adjustment circuit connected to a source of the eighth transistor.

12. The semiconductor device according to claim 11 , wherein
the second potential adjustment circuit includes
an eleventh transistor which is connected to a source of the eighth transistor in parallel with the ninth transistor and which is diode-connected through the eighth transistor.

13. The semiconductor device according to claim 8 , wherein
the first differential amplifier circuit further includes
a twelfth transistor which forms a third current mirror circuit with the fourth transistor and which forms a fourth current mirror circuit with the eighth transistor, and

the first differential amplifier circuit generates a first output signal in response to a signal transferred through the fifth transistor, and generates a second output signal logically inverted from the first output signal in response to a signal transferred through the twelfth transistor.

14. The semiconductor device according to claim 1 , wherein
the first differential amplifier circuit further includes:
a first input transistor which is connected to the drain of the first transistor and which receives a first input signal at a gate;
a second input transistor which is connected to the drain of the second transistor and which receives a reference signal at a gate; and
a variable current circuit which is connected to a source of the first input transistor and a source of the second input transistor and which changes a current amount in accordance with a polarity of the first input signal.

15. The semiconductor device according to claim 1 , further comprising:
a first inverter which has an input node connected to a source of the fifth transistor; and
a first capacitive element which has one end connected to an output node of the first inverter and another end connected to a line connecting a gate of the fifth transistor and a gate of the sixth transistor.

16. The semiconductor device according to claim 1 , further comprising
a second differential amplifier circuit of which polarity is inverted from a polarity of the first differential amplifier circuit,
wherein the first differential amplifier circuit includes:
a first input transistor which is connected to the drain of the first transistor and which receives a first input signal at a gate; and
a second input transistor which is connected to the drain of the second transistor and which receives a reference signal at a gate, and

the second differential amplifier circuit includes:
a thirteenth transistor;
a fourteenth transistor of which gate and drain are connected to the thirteenth transistor;
a fifteenth transistor diode-connected through the thirteenth transistor;
a sixteenth transistor diode-connected through the fourteenth transistor;
a seventeenth transistor which forms a fifth current mirror circuit with the fifteenth transistor;
an eighteenth transistor which is connected to a drain of the thirteenth transistor in parallel with the fifteenth transistor and which forms a sixth current mirror circuit with the seventeenth transistor;
a third input transistor which is connected to the drain of the thirteenth transistor and which receives the first input signal at a gate; and
a fourth input transistor which is connected to a drain of the fourteenth transistor and which receives the reference signal at a gate.

17. The semiconductor device according to claim 16 , further comprising:
a first inverter which has an input node connected to a source of the fifth transistor and a source of the seventeenth transistor;
a first capacitive element which has one end connected to an output node of the first inverter and another end connected to a line connecting a gate of the fifth transistor and a gate of the sixth transistor; and
a second capacitive element which has one end connected to the output node of the first inverter and another end connected to a line connecting a gate of the seventeenth transistor and a gate of the fifteenth transistor.

18. The semiconductor device according to claim 13 , further comprising
a second differential amplifier circuit of which polarity is inverted from a polarity of the fi

Assignees

• Toshiba Memory Corp

Inventors

• Yasuda Yohei

Classifications

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• H03F3/45264

  Complementary cross coupled types · CPC title

• H03F3/45219 Primary

  Folded cascode stages · CPC title

• H03F3/45237

  Complementary long tailed pairs having parallel inputs and being supplied in series · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title