Sensing circuits for use in low power nanometer flash memory devices

Patent metadata

Field	Value
Publication number	US-9355734-B2
Application number	US-201414196839-A
Country	US
Kind code	B2
Filing date	Mar 4, 2014
Priority date	Mar 4, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.

First claim

What is claimed is:

1. A sensing circuit for use in a memory device, comprising:
a memory data read block for sensing a selected memory cell;
a memory reference read block for sensing a reference memory cell;
a differential amplifier block comprising a first capacitor comprising a first terminal and a second terminal, a second capacitor comprising a first terminal and a second terminal, a precharge circuit for charging the second terminal of the first capacitor and the second terminal of the second capacitor prior to a sensing operation, and an output;
wherein the first terminal of the first capacitor is connected to the memory data read block and the second terminal of the first capacitor is connected to the differential amplifier block and the first terminal of the second capacitor is connected to the memory reference read block and the second terminal of the second capacitor is connected to the differential amplifier block;
wherein during the sensing operation the output of the differential amplifier block indicates a value stored in the selected memory cell.

2. The sensing circuit of claim 1 , wherein the selected memory cell is a split gate flash memory cell.

3. The sensing circuit of claim 2 , wherein the reference memory cell is a split gate flash memory cell.

4. The sensing circuit of claim 1 , wherein the precharge circuit comprises a plurality of switches that turn on before the sensing operation and turn off during the sensing operation.

5. The sensing circuit of claim 4 , wherein one of the plurality of switches when turned on connects a sensed node of the memory data read block to a voltage source.

6. The sensing circuit of claim 5 , wherein one of the plurality of switches when turned on connects a sensed node of the memory reference read block to a voltage source.

7. The sensing circuit of claim 1 , wherein the memory data read block comprises a current source, a cascading sensing NMOS transistor, a bitline clamp NMOS transistor, and a diode connected sensing load PMOS transistor.

8. The sensing circuit of claim 7 , wherein the memory reference read block comprises a current source, a reference bitline clamp NMOS transistor, a cascading sensing NMOS transistor, and a diode connected sensing load PMOS transistor.

9. The sensing circuit of claim 8 , wherein the differential amplifier block further comprises input differential pair NMOS transistors, current mirror load PMOS transistors, and output PMOS transistor, a current bias NMOS transistor, and an output current bias NMOS transistor.

10. The sensing circuit of claim 1 , wherein the differential amplifier includes a cross coupled inverter pair in the differential input path.

11. The sensing circuit of claim 1 , wherein the memory reference read block supplies a replica reference bias.

12. A method of determining the value stored in a selected memory cell, comprising:
precharging a first terminal of a first capacitor and a first terminal of a second capacitor using a precharge circuit;
sensing a selected memory cell at a sensed node using a memory data read block;
sensing a reference memory cell at a reference node using a memory reference read block;
comparing the sensed node and the reference node using the differential amplifier block, the differential amplifier block comprising the first capacitor, the second capacitor, and an output, and wherein a second terminal of the first capacitor is connected to the memory data read block and the first terminal of the first capacitor is connected to the differential amplifier block and a second terminal of the second capacitor is connected to the memory reference read block and the first terminal of the second capacitor is connected to the differential amplifier block; and
indicating at the output of the differential amplifier block a value stored in the selected memory cell.

13. The method of claim 12 , wherein the selected memory cell is a split gate flash memory cell.

14. The method of claim 13 , wherein the reference memory cell is a split gate flash memory cell.

15. The method of claim 12 , wherein the precharge circuit comprises a plurality of switches, and wherein the precharging step comprises turning on the plurality of switches.

16. The method of claim 15 , wherein the precharging step comprises connecting the sensed node of the memory data read block to a voltage source.

17. The method of claim 16 , wherein precharging step further comprises connecting the sensed node of the reference read block to a voltage source.

18. The method of claim 12 , wherein the memory data read block comprises a current source, a cascading sensing NMOS transistor, a bitline clamp NMOS transistor, and a diode connected sensing load PMOS transistor.

19. The method of claim 18 , wherein the memory reference read block comprises a current source, a reference bitline clamp NMOS transistor, a cascading sensing NMOS transistor, and a diode connected sensing load PMOS transistor.

20. The method of claim 19 , wherein the differential amplifier block further comprises input differential pair NMOS transistors, current mirror load PMOS transistors, an output PMOS transistor, a current bias NMOS transistor, and an output current bias NMOS transistor.

21. A method of determining a value stored in a selected memory cell, comprising:
precharging a first terminal of a first capacitor and a first terminal of a second capacitor using a precharge circuit;
sensing a selected memory cell at a sensed node using a memory data read block;
sensing a reference memory cell at a reference node using a memory reference read block;
comparing the sensed node and the reference node during a ramping period using the differential amplifier block, the differential amplifier block comprising the first capacitor, the second capacitor, and an output, wherein a second terminal of the first capacitor is connected to the memory data read block and the first terminal of the first capacitor is connected to the differential amplifier block and a second terminal of the second capacitor is connected to the memory reference read block and the first terminal of the second capacitor is connected to the differential amplifier block; and
indicating at the output of the differential amplifier block the value stored in the selected memory cell.

22. The method of claim 21 , wherein the selected memory cell is a split gate flash memory cell.

23. The method of claim 21 , wherein the sensed node is ramping down in the sensing period.

24. The method of claim 21 , wherein the reference node is ramping up in the sensing period.

25. The method of claim 21 , wherein the differential amplifier block comprises a comparator.

26. The method of claim 25 , wherein the comparator is a single comparator.

Assignees

• Silicon Storage Tech Inc

Inventors

• Tran Hieu Van
• Nguyen Hung Quoc
• Ly Anh
• Vu Thuan

Classifications

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C16/0425

  comprising cells containing a merged floating gate and select transistor · CPC title

• G11C2216/04

  Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title