Electronic circuit for fast temperature sensing of a power switching device

Patent metadata

Field	Value
Publication number	US-10819102-B2
Application number	US-201815863182-A
Country	US
Kind code	B2
Filing date	Jan 5, 2018
Priority date	Aug 8, 2016
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

An electronic circuit for sensing a temperature rise in a power transistor device, the temperature rise caused by a current flow in the power transistor device. The power transistor device and a sense-FET are disposed on a substrate. The sense-FET senses a fractional portion of the current flow and outputs a current signal. A JFET has its drain connected to the drain of the power transistor device. The gate of the JFET is connected to the source of the power transistor device, such that when the power transistor device is on, the JFET is also turned on, and a drain voltage signal of the power transistor device is output at a second node of the JFET. A detection circuit receives the drain voltage signal and the current signal and outputs an alarm signal when the drain-source resistance of the power transistor device exceeds a combined threshold limit.

First claim

I claim:

1. An electronic circuit for detecting a temperature rise in a power transistor device, the temperature rise caused by a current flow in the power transistor device, the electronic circuit comprising:
a sense-field-effect transistor (sense-FET), the sense-FET sensing a fractional portion of the current flow and outputting a current signal at a first node;
a normally-on switching transistor device, a drain of the normally-on switching transistor device being coupled to a drain of the power transistor device, a gate of the normally-on switching transistor device being connected to a source of the power transistor device, such that when the power transistor device is turned on, the normally-on switching transistor device is also turned on, and a drain voltage signal of the power transistor device is output at a second node; and
a detection circuit coupled to receive the drain voltage signal and the current signal, the detection circuit outputting an alarm signal when the drain voltage signal exceeds a reference voltage signal and the current signal exceeds a reference current signal, which indicates that a drain-source resistance of the power transistor device exceeds a combined threshold limit.

2. The electronic circuit of claim 1 wherein the power transistor device comprises a GaN high electron mobility junction field-effect transistor (HEMT) cascaded with a Si power MOSFET, the drain of the GaN HEMT being coupled to the drain of the normally-on switching transistor device.

3. The electronic circuit of claim 2 wherein the normally-on switching transistor device comprises a junction field-effect transistor (JFET).

4. The electronic circuit of claim 3 wherein the gate of the JFET is coupled to the source of the Si power MOSFET.

5. The electronic circuit of claim 4 wherein the gate of the JFET and the source of the Si power MOSFET are both connected to a ground potential.

6. The electronic circuit of claim 1 wherein the alarm signal indicates that the temperature rise exceeds a thermal threshold of the power transistor device.

7. The electronic circuit of claim 2 wherein the GaN HEMT is disposed on a first semiconductor die and the Si power MOSFET is disposed on a second semiconductor die.

8. The electronic circuit of claim 7 wherein the first semiconductor die comprises sapphire and the second semiconductor die comprises silicon.

9. The electronic circuit of claim 1 wherein the reference current signal is set to a value at which point the current flow in the power transistor device has reached a calibration current threshold.

10. The electronic circuit of claim 2 wherein the reference current signal is set to a value at which point the current flow in the power transistor device has reached a calibration current threshold.

11. The electronic circuit of claim 1 wherein the reference voltage signal is set to a value at which point the drain-source resistance has reached a calibration threshold value of the drain voltage signal indicative of temperature limit of the power transistor device.

12. The electronic circuit of claim 2 wherein the reference voltage signal is set to a value at which point the drain-source resistance has reached a calibration threshold value of the drain voltage signal indicative of temperature limit of the power transistor device.

13. The electronic circuit of claim 1 wherein the detection circuit comprises:
a first comparator having a first input coupled to receive the drain voltage signal, and a second input coupled to receive the reference voltage signal, the first comparator outputting a first logic signal when the drain voltage signal exceeds the reference voltage signal; and
a second comparator having a first input coupled to receive the current signal, and a second input coupled to receive the reference current signal, the second comparator outputting a second logic signal when the current signal exceeds the reference current signal.

14. The electronic circuit of claim 2 wherein the detection circuit comprises:
a first comparator having a first input coupled to receive the drain voltage signal, and a second input coupled to receive the reference voltage signal, the first comparator outputting a first logic signal when the drain voltage signal exceeds the reference voltage signal; and
a second comparator having a first input coupled to receive the current signal, and a second input coupled to receive the reference current signal, the second comparator outputting a second logic signal when the current signal exceeds the reference current signal.

15. The electronic circuit of claim 13 wherein the detection circuit further comprises a flip-flop having an input coupled to receive the first logic signal, a clock input coupled to receive the second logic signal, the flip-flop outputting the alarm signal responsive to the first and second logic signals.

16. The electronic circuit of claim 14 wherein the detection circuit further comprises a flip-flop having an input coupled to receive the first logic signal, a clock input coupled to receive the second logic signal, the flip-flop outputting the alarm signal responsive to the first and second logic signals.

17. The electronic circuit of claim 15 wherein the flip-flop is a D-type flip-flop.

18. The electronic circuit of claim 16 wherein the flip-flop is a D-type flip-flop.

19. The electronic circuit of claim 1 further comprising a sense resistor coupled between the first node and a ground potential.

20. The electronic circuit of claim 2 further comprising a sense resistor coupled between the first node and a ground potential.

21. The electronic circuit of claim 1 wherein the first node comprises the source of the sense-FET and the second node is the source of the normally-on switching transistor device.

22. The electronic circuit of claim 2 wherein the first node comprises the source of the sense-FET and the second node is the source of the normally-on switching transistor device.

23. The electronic circuit of claim 1 wherein the gate of the normally-on switching transistor device and the source of the power transistor device are both connected to a ground potential.

24. The electronic circuit of claim 1 wherein the drain of the power transistor device is coupled to a power converter energy transfer element.

25. The electronic circuit of claim 1 wherein the alarm signal is used to turn off the power transistor device.

26. The electronic circuit of claim 2 wherein the alarm signal is used to turn off the power transistor device.

27. The electronic circuit of claim 1 wherein the detection circuit receives the voltage signal and the current signal at a predetermined gate-source voltage, and a predetermined current flow in the power transistor device.

28. The electronic circuit of claim 2 wherein the detection circuit receives the voltage signal and the current signal at a predetermined gate-source voltage, and a predetermined current flow in the power transistor device.

Assignees

• Power Integrations Inc

Inventors

• Mayell Robert

Classifications

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D30/83

  FETs having PN junction gate electrodes · CPC title