Magnetic flux-to-voltage transducer based on Josephson junction arrays

Patent metadata

Field	Value
Publication number	US-10818833-B2
Application number	US-201916256826-A
Country	US
Kind code	B2
Filing date	Jan 24, 2019
Priority date	Nov 20, 2014
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A device and method for converting magnetic flux to voltage uses a linear Fraunhofer pattern of a 1D array of long Josephson junctions. The 1D array of Josephson junctions may include from 1 to 109 junctions formed in a planar geometry with a bridge width within the range of 4-10 μm.

First claim

The invention claimed is:

1. A method for converting magnetic flux to voltage comprising using a one-dimensional planar array of long Josephson junctions on a substrate, wherein the planar array is configured in a geometry selected from line, spiral, circle, meandering line, and combinations thereof, wherein each long Josephson junction has a bridge width greater than two times the Josephson penetration depth.

2. The method of claim 1 , wherein the planar geometry comprises a meandering line comprising from 10 to 10 6 meanders.

3. The method of claim 1 , wherein the array of Josephson junctions comprises from 1 to 10 9 junctions.

4. The method of claim 1 , wherein the Josephson junctions have a bridge width within a range of 4 to 100 μm.

5. The method of claim 4 , wherein the Josephson junctions have a junction width much narrower than the bridge width.

6. The method of claim 1 , wherein the Josephson junctions have a bridge width within a range of 4 to 10 μm.

7. The method of claim 1 , wherein the array is arranged in series, parallel, or series-parallel.

8. The method of claim 1 , wherein the array of Josephson junctions is formed from an YBCO superconductor.

9. The method of claim 1 , wherein the array of Josephson junctions is formed in a superconducting material selected from the group consisting of Nb, Pb, Al, MgB 2 , and cuprates.

10. The method of claim 1 , wherein the Josephson junctions comprise junction barriers selected from the group consisting of Superconductor-Insulator-Superconductor (SIS), Superconductor-Normal Metal-Superconductor (SNS), and Superconductor-diminished superconductor-Superconductor (SS′S).

11. The method of claim 1 , wherein the Josephson junctions comprise a junction selected from the group consisting of ion damage Josephson junctions, SIS trilayers, step-edge junctions, bicrystal junctions, grain boundary junctions, and ramp junctions.

12. A method for converting magnetic flux to voltage comprising using a Fraunhofer pattern of a 1D array of long Josephson junctions.

13. The method of claim 12 , wherein the ID array of long Josephson junctions is configured in a planar geometry selected from line, spiral, circle, meandering line, and combinations thereof.

14. The method of claim 12 , wherein the array comprises from 1 to 10 9 long Josephson junctions.

15. The method of claim 12 , wherein the Josephson junctions have a junction width much narrower than the bridge width.

16. The method of claim 12 , wherein the junction width is less than 10 μm and the bridge width is in a range of 50 to 100 μm.

17. The method of claim 12 , wherein the array is arranged in series, parallel, or series-parallel.

18. The method of claim 12 , wherein the array of Josephson junctions is formed in a superconducting material selected from the group consisting of Nb, Pb, Al, MgB 2 , and cuprates.

19. The method of claim 12 , wherein the Josephson junctions comprise junction barriers selected from the group consisting of Superconductor-Insulator-Superconductor (SIS), Superconductor-Normal Metal-Superconductor (SNS), and Superconductor-diminished superconductor-Superconductor (SS′S).

20. The method of claim 12 , wherein the Josephson junctions comprise a junction selected from the group consisting of ion damage Josephson junctions, SIS trilayers, step-edge junctions, bicrystal junctions, grain boundary junctions, and ramp junctions.

Assignees

• Univ California

Inventors

• Cybart Shane A
• Wong Travis J
• Dynes Robert C
• Cho Ethan Y

Classifications

• H01L39/225

  Electricity · mapped topic

• H01L39/025 Primary

  Electricity · mapped topic

• H01L27/18

  Electricity · mapped topic

• H10N69/00 Primary

  Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 · CPC title

• H10N60/124

  comprising high-Tc ceramic materials · CPC title