Circuitry for one-transistor synapse cell and operation method of the same

Patent metadata

Field	Value
Publication number	US-10818333-B2
Application number	US-201916550809-A
Country	US
Kind code	B2
Filing date	Aug 26, 2019
Priority date	Sep 27, 2017
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

First claim

What is claimed is:

1. A memory circuit comprising:
a plurality of word lines;
a plurality of bit lines intersecting said plurality of word lines at a plurality of cross points;
a plurality of signal lines; and
a plurality of single memory transistor synapse cells located at said plurality of cross points, each of said cells in turn comprising:
a memory transistor having a gate;
a pulse shaping unit coupled to a given one of said signal lines and said gate of said memory transistor;
an AND gate having inputs coupled to a corresponding one of said word lines and a corresponding one of said bit lines, and having an output coupled to said pulse shaping unit; and
a pass gate arrangement coupled to said memory transistor, said corresponding one of said word lines, and said corresponding one of said bit lines, and said pass gate arrangement comprising three transistors, each gate of said three transistors connected directly to said output of said AND gate;
wherein said pulse shaping unit, said AND gate, and said pass gate arrangement are cooperatively configured to apply pulses to said gate of said memory transistor for weight adjustment during an update operation and to interconnect said memory transistor to said corresponding one of said bit lines during an inference operation.

2. The memory circuit of claim 1 , wherein said memory transistors comprise at least one of ferroelectric field effect transistors, floating-gate transistors, and charge-trapping-gate transistors.

3. The memory circuit of claim 1 , further comprising a control circuit block coupled to said word line, said bit line, and said signal line, and configured to:
during an inference operation, set said bit line to logical zero causing said AND gate to output a logical zero to turn on said first and second pass gate p-type field effect transistors and causing said pulse shaping unit to apply a fixed read voltage to said gate of said memory transistor; and
during an update operation, cause binary input on said word line and said bit line such that when said word line and said bit line both have a logical one value, said AND gate outputs a logical one to turn off said first and second pass gate p-type field effect transistors and turn on said pass gate n-type field effect transistor to ground said first drain-source terminal of said memory transistor, and cause said signal lines to control said pulse shaping unit to apply at least one of positive pulses to increase a weight and negative pulses to decrease said weight.

4. A method comprising:
providing a memory circuit, said memory circuit in turn comprising:
a plurality of word lines;
a plurality of bit lines intersecting said plurality of word lines at a plurality of cross points;
a plurality of signal lines; and
a plurality of single memory transistor synapse cells located at said plurality of cross points, each of said cells in turn comprising:
a memory transistor having a gate;
a pulse shaping unit coupled to a given one of said signal lines and said gate of said memory transistor;
an AND gate having inputs coupled to a corresponding one of said word lines and a corresponding one of said bit lines, and having an output coupled to said pulse shaping unit; and
a pass gate arrangement coupled to said memory transistor, said corresponding one of said word lines, and said corresponding one of said bit lines, and said pass gate arrangement comprising three transistors, each gate of said three transistors connected directly to said output of said AND gate;

generating a signal on said gates of said three transistors to configure said memory transistor for performing an update operation;
applying pulses to said gate of said memory transistor for weight adjustment during said update operation, using said pulse shaping unit, said AND gate, and said pass gate arrangement; and
interconnecting said memory transistor to said corresponding one of said bit lines during an inference operation, using said pulse shaping unit, said AND gate, and said pass gate arrangement.

Assignees

• IBM

Inventors

• Han Jin Ping
• Sun Xiao
• Yang Teng

Classifications

• G06N3/08

  Learning methods · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• H03K19/094

  using field-effect transistors · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title