Configurable interface card

Patent metadata

Field	Value
Publication number	US-10817443-B2
Application number	US-201916264320-A
Country	US
Kind code	B2
Filing date	Jan 31, 2019
Priority date	Mar 28, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

An apparatus supporting a plurality of operational modes includes a physical interface having a plurality of lanes, an endpoint device having a plurality of interfaces, a plurality of multiplexers disposed between the physical interface and the endpoint device, and a controller configured to route a first portion of the lanes to a first portion of the interfaces through the multiplexers in response to a selected mode of the plurality of operational modes.

First claim

What is claimed is:

1. An apparatus supporting a plurality of operational modes, the apparatus comprising:
a physical interface including a plurality of lanes, a physical access attachment (PMA) layer coupled to the lanes, and a physical coding sublayer (PCS), the plurality of lanes being configured to connect to a connector;
an endpoint device including a plurality of interfaces;
a plurality of multiplexers disposed between the physical interface and the endpoint device; and
a controller configured to route a first portion of the lanes to a first portion of the interfaces through the multiplexers in response to a selected mode of the plurality of operational modes.

2. The apparatus of claim 1 , wherein the multiplexers are digital multiplexers disposed between the PMA layer and the PCS.

3. The apparatus of claim 1 , wherein the multiplexers are digital multiplexers disposed between the PCS and the interfaces.

4. The apparatus of claim 1 , wherein the interfaces conform to a PHY interface for PCI Express Architecture (PIPE) specification.

5. The apparatus of claim 1 , wherein a portion of the lanes forms at least one PCI Express (PCIe) link.

6. The apparatus of claim 5 , wherein the at least one PCIe link comprises one of a ×32, ×16, ×8, ×4, ×2, and ×1 lane width.

7. The apparatus of claim 1 , wherein the endpoint device comprises a first endpoint block configured to provide the first portion of the lanes to a first link and a second endpoint block configured to provide a second portion of the lanes to a second link.

8. The apparatus of claim 7 , wherein the first link comprises one of a ×32, ×16, ×8, ×4, ×2, and ×1 lane width, and the second link comprises one of a ×32, ×16, ×8, ×4, ×2, and ×1 lane width.

9. The apparatus of claim 1 , wherein the connector comprises a plurality of pins configured to couple the physical interface to a PCIe slot on a motherboard or backplane.

10. The apparatus of claim 9 , wherein the plurality of pins comprise configuration pins coupled to the controller and configured to provide electrical signals defining the selected mode of the plurality of operational modes.

11. The apparatus of claim 1 , wherein the controller comprises a software program stored in a memory device, the software program comprising instructions executable by the controller to perform a reassignment of a portion of the lanes to a portion of the interfaces using the multiplexers based on the selected mode of the plurality of operational modes.

12. The apparatus of claim 9 , wherein the controller is further configured to assign a lane 0 (zero) to a pin of the plurality of pins based on the selected mode.

13. The apparatus of claim 1 , wherein the operational modes comprise one of a U.2 single port, a U.2 dual port, a U.3 single port, and a U.3 dual port.

14. The apparatus of claim 1 , wherein the controller performs a regrouping of the interfaces and a logical-to-physical lane reassignment of the regrouped interfaces through the multiplexers in response to a change of the selected mode.

15. The apparatus of claim 1 , wherein the physical interface further comprises a clock synchronizer configured to synchronize a clock signal of the plurality of lanes.

16. A method for assigning lanes of a physical interface to interfaces of an apparatus having a plurality of lanes coupled to an endpoint device having the interfaces through a plurality of multiplexers, the apparatus supporting a plurality of operational modes, the method comprising:
determining a selected mode of the plurality of operational modes;
grouping the interfaces into one or more links in response to the selected mode; and
assigning the one or more links to a location of the physical interface through the multiplexers by a controller,
wherein the physical interface comprises a physical access attachment (PMA) layer coupled to the lanes, and a physical coding sublayer (PCS),
wherein the lanes are configured to connect to a connector, and the multiplexers are disposed between the PMA layer and the PCS or between the PCS and the interfaces.

17. The method of claim 16 , wherein the one or more links each comprise one of a ×32, ×16, ×8, ×4, ×2, and ×1 lane width.

18. The method of claim 16 , wherein determining the selected mode comprises:
providing electrical signals of configuration pins of the connector to the controller.

19. The method of claim 16 , wherein the one or more links each comprise an equal lane width.

20. The method of claim 16 , wherein the one or more links each comprise an unequal lane width.

Assignees

• Sk Hynix Inc

Inventors

• Mao Jinliang
• Lee Jongsu

Classifications

• G06F13/20 Primary

  for access to input/output bus · CPC title

• G06F2213/0026

  PCI express · CPC title

• H01R29/00

  Coupling parts for selective co-operation with a counterpart in different ways to establish different circuits, e.g. for voltage selection, for series-parallel selection, {programmable connectors} · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title