Flip chip bonding onto a photonic integrated circuit

Patent metadata

Field	Value
Publication number	US-10816740-B2
Application number	US-201916265198-A
Country	US
Kind code	B2
Filing date	Feb 1, 2019
Priority date	Feb 1, 2019
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

Conventional hybrid photonic integrated circuits (PIC) combine one type of semiconductor platform for the main PIC, and a different type of semiconductor platform for a secondary chip. Conventional mounting processes include forming a recess in the main PIC, and mating electrical connectors from the secondary chip and the main PIC within the recess. Mating the first and second electrical connectors in the recess increases the complexity of forming the main PIC, and hampers heat dissipation from secondary chip through oxide layers in the main PIC. Providing a conductive, e.g. redistribution, layer from the first electrode along the bottom and sides of the recess eliminates the complexity in forming the main PIC, and enables the first electrical connector to be mounted directly onto a more thermally conductive substrate material.

First claim

We claim:

1. A hybrid photonic integrated circuit (PIC) comprising:
a main photonic integrated circuit (PIC), including a first waveguide, an electrical connector for transmitting electrical signals from an external source, and a first electrode mounted in a recess therein;
a secondary device mounted in the recess, including a second waveguide, aligned with the first waveguide, and a second electrode connected to the first electrode;
a conductive layer extending from the first electrode along a bottom of the recess out from underneath the secondary device, and electrically connected to the electrical connector;
a first alignment feature extending from the bottom of the recess and spaced apart from the first waveguide; and
a second alignment feature on the secondary device spaced apart from the second waveguide in contact with the first alignment feature;
wherein the first electrode and/or the second electrode comprises a stack of conductive metal layers extending from the conductive layer at the bottom of the recess to the secondary device.

2. The hybrid PIC according to claim 1 , wherein the electrical connector comprises an electrical pad on an upper surface of the main PIC vertically spaced from the bottom of the recess; and wherein the conductive layer extends along the bottom of the recess and a sidewall of the recess into contact with the electrical pad.

3. The hybrid PIC according to claim 2 , wherein the sidewall of the recess is at an obtuse angle to the bottom of the recess; and
wherein the obtuse angle is between 95° and 120°.

4. A hybrid photonic integrated circuit (PIC) comprising:
a main photonic integrated circuit (PIC), including a first waveguide, an electrical connector for transmitting electrical signals from an external source, and a first electrode mounted in a recess therein;
a secondary device mounted in the recess, including a second waveguide, aligned with the first waveguide, and a second electrode connected to the first electrode; and
a conductive layer extending from the first electrode along a bottom of the recess out from underneath the secondary device, and electrically connected to the electrical connector;
wherein the electrical connector comprises an electrical pad on an upper surface of the main PIC, and a conductive wire bond extending from the conductive layer on the bottom of the recess to the electrical pad on the upper surface of the main PIC.

5. A hybrid photonic integrated circuit (PIC) comprising:
a main photonic integrated circuit (PIC), including a first waveguide, an electrical connector for transmitting electrical signals from an external source, and a first electrode mounted in a recess therein;
a secondary device mounted in the recess, including a second waveguide, aligned with the first waveguide, and a second electrode connected to the first electrode; and
a conductive layer extending from the first electrode along a bottom of the recess out from underneath the secondary device, and electrically connected to the electrical connector;
wherein the electrical connector comprises a conductive wire bond extending from the conductive layer.

6. The hybrid PIC according to claim 5 , wherein the first electrode comprises a stack of conductive metal layers.

7. The hybrid PIC according to claim 1 , wherein the secondary device includes a gain medium comprised of a Group III-V material; and wherein the main PIC comprises a silicon photonic integrated circuit.

8. The hybrid PIC according to claim 1 , wherein the main PIC comprises a multi-layer structure, including the first waveguide, and cladding layer, mounted on a substrate;
wherein the substrate comprises a material more thermally conductive than the cladding layer; and
wherein the recess extends through the cladding layer to the substrate, whereby the first electrode is mounted on the substrate.

9. The hybrid PIC according to claim 5 , further comprising:
a first alignment feature on the main photonic integrated circuit; and
a second alignment feature on the secondary device in contact with the first alignment feature.

10. The hybrid PIC according to claim 9 , wherein the first alignment feature comprises a surface of the first waveguide, and the second alignment feature comprises a surface at or close to the second waveguide.

Assignees

• Elenion Tech Llc

Inventors

• Novack Ari
• Fathololoumi Saeed
• Caverley Michael

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• G02B6/4274 Primary

  Electrical aspects (G02B6/4263 and G02B6/4265 take precedence) · CPC title