Electronic module having an electrically insulating structure with material having a low modulus of elasticity

US10813229B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10813229-B2
Application numberUS-201514882678-A
CountryUS
Kind codeB2
Filing dateOct 14, 2015
Priority dateOct 16, 2014
Publication dateOct 20, 2020
Grant dateOct 20, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Electronic module comprising at least one electronic chip, an encapsulation structure in which the at least one electronic chip is at least partially encapsulated, an electrically conductive structure for the electrically conductive contacting of the at least one electronic chip, and an electrically insulating structure which is at least partially formed from a material having a low modulus of elasticity, wherein a variation of the value of the modulus of elasticity is at the most 10 GPa in a temperature range between −40° C. and +150° C.

First claim

Opening claim text (preview).

What is claimed is: 1. Electronic module, comprising: at least one electronic chip; an encapsulation structure, in which the at least one electronic chip is at least partially encapsulated; an electrically conductive structure for the electrically conductive contacting of the at least one electronic chip; and an electrically insulating structure which is at least partially formed of a material having a low modulus of elasticity; wherein a variation of the value of the modulus of elasticity is at the most 10 GPa over a temperature range between −40° C. and +150° C.; wherein the electrically conductive structure and the electrically insulating structure form a laminated sequence of layers, on whose one main surface the at least partially encapsulated at least one electronic chip is arranged and on whose other main surface the electronic module can be mounted on an electronic peripheral device; and wherein the electrically conductive structure is embedded as rewiring in the electrically insulating structure, so that the electrically conductive structure and the electrically insulating structure form a redistribution layer. 2. Electronic module according to claim 1 , wherein the material having a low modulus of elasticity has a value of the modulus of elasticity of at the most 16 GPa at −40° C. 3. Electronic module according to claim 1 , wherein the material having a low modulus of elasticity has a value of the modulus of elasticity of at the most 5 GPa over the entire temperature range between −40° C. and +150° C. 4. Electronic module according to claim 1 , wherein the material having a low modulus of elasticity is selected from a group consisting of Taconics TSM-DS3, Taconics FastFilm, Panasonic LCP R-F705T, and Rogers 3003. 5. Electronic module according to claim 1 , configured as a ball grid array module, in particular as an embedded wafer level ball grid array module, or wafer level package. 6. Electronic module according to claim 1 , wherein the electrically insulating structure has another material having a higher modulus of elasticity, in particular a resin-fiber glass mixture, more particularly FR-4. 7. Electronic module according to claim 6 , wherein at least a part of the other material having the higher modulus of elasticity is arranged between the at least partially encapsulated at least one electronic chip on the one hand and the material having the low modulus of elasticity on the other hand. 8. Electronic module according to claim 7 , comprising at least one bonding wire at least partially encapsulated in the encapsulation structure for the electrically conductive coupling of at least one chip pad on a top side of at least one electronic chip with the electrically conductive structure on a bottom side of the at least one electronic chip. 9. Electronic module according to claim 6 , wherein at least a part of the material having the low modulus of elasticity is arranged between the at least partially encapsulated at least one electronic chip on the one hand and the other material having the higher modulus of elasticity on the other hand. 10. Electronic module according to claim 9 , the at least one electronic chip being mounted in flip chip technology and comprising a bottom side; the electronic module further comprising at least one chip pad ( 170 ) on the bottom side of the at least one electronic chip mounted in flip chip technology, which is electrically conductively coupled to at least one chip pad on the bottom side to the electrically conductive structure. 11. Electronic module according to claim 1 , wherein the electrically conductive structure is embedded as a redistribution wiring in the electrically insulating structure, so that the electrically conductive structure and the electrically insulating structure form a redistribution layer, on whose one main surface the at least one electronic chip and the encapsulation structure adjoin and on whose other main surface the electronic module can be mounted on an electronic peripheral device. 12. Electronic module according to claim 11 , wherein the entire electrically insulating structure of the redistribution layer is formed from the material having the low modulus of elasticity. 13. Electronic module according to claim 11 , wherein the electrically insulating structure of the redistribution layer has, in addition to the material having the low modulus of elasticity, other material having a higher modulus of elasticity. 14. Electronic module according to claim 13 , wherein the other material having the higher modulus of elasticity is arranged between the at least one electronic chip at least partially encapsulated with the encapsulation structure on the one hand and the material having the low modulus of elasticity on the other hand. 15. Electronic module according to claim 1 , wherein on the other main surface at least one solder structure is arranged, in particular a plurality of solder beads. 16. Electronic arrangement, comprising: at least one electronic module according to claim 1 ; an electronic peripheral device on which the at least one electronic module is mounted such that the at least one electronic chip is electrically conductively coupled to the electronic peripheral device by the electrically conductive structure. 17. Electronic arrangement according to claim 16 , wherein the electronic peripheral device has an electrically insulating structure which is at least partially formed of a material having a low modulus of elasticity. 18. Method for producing an electronic module, wherein the method comprises: at least partial encapsulating at least one electronic chip with an encapsulation structure; forming an electrically conductive structure for the electrically conductive contacting of the at least one electronic chip; and forming an electrically insulating structure at least partially made of a material having a low modulus of elasticity; wherein a variation of the value of the modulus of elasticity is at the most 10 GPa over a temperature range between −40° C. and +150° C.; wherein the electrically conductive structure and the electrically insulating structure form a laminated sequence of layers, on whose one main surface the at least partially encapsulated at least one electronic chip is arranged and on whose other main surface the electronic module can be mounted on an electronic peripheral device; and wherein the electrically conductive structure is embedded as rewiring in the electrically insulating structure, so that the electrically conductive structure and the electrically insulating structure form a redistribution layer.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • the substrate having spherical bumps for external connection · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

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What does patent US10813229B2 cover?
Electronic module comprising at least one electronic chip, an encapsulation structure in which the at least one electronic chip is at least partially encapsulated, an electrically conductive structure for the electrically conductive contacting of the at least one electronic chip, and an electrically insulating structure which is at least partially formed from a material having a low modulus of …
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W70/695. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 20 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).