Process for hard mask development for MRAM pillar formation using photolithography

Patent metadata

Field	Value
Publication number	US-10811594-B2
Application number	US-201715857351-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A method for fabricating an array of pillars. The method includes fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer. The method selects between subsequent electron beam patterning for the wafer and photolithography patterning for the wafer. For electron beam patterning, an electron beam lithography hard mask is deposited onto the metal stack, and an electron beam is used to pattern a first array of pillars into the electron beam lithography hard mask to produce a first resulting pillar array. For photolithography patterning, a photolithography hard mask is deposited onto the metal stack, and photolithography is used to pattern a second array of pillars into the photolithography hard mask to produce a second resulting pillar array. The first resulting pillar array is substantially the same as the second resulting pillar array.

First claim

What is claimed is:

1. A method for fabricating an array of pillars, the method comprising:
performing an MTJ manufacturing process comprising:
fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer;
depositing a photolithography hard mask onto the metal stack;
selecting a manufacturing process to pattern an array of pillars on the photolithography hard mask from a plurality of manufacturing processes based on a maturity level of the MTJ manufacturing process, the plurality of manufacturing processes comprising:
a first manufacturing process that uses photolithography to pattern the array of pillars into the photolithography hard mask to produce a resulting pillar array, wherein the first manufacturing process is configured for a high-volume production phase; and
a second manufacturing process that uses electron beam patterning to pattern the array of pillars into the photolithography hard mask to produce the resulting pillar array, wherein the second manufacturing process is configured for a research and development phase; and

performing the selected manufacturing process to produce the resulting pillar array on the photolithography hard mask.

2. The method of claim 1 , wherein reactive ion etching (REI) etches the photolithography hard mask to form hard mask pillars on top of the metal stack.

3. The method of claim 1 , wherein the photolithography hard mask comprises a multilayer photolithography hard mask comprising a bottom antireflective coating (BARC) layer, a first hard mask layer, and a second hard mask layer.

4. The method of claim 3 , wherein the first hard mask layer comprises tantalum nitride and the second hard mask layer comprises silicon oxide.

5. The method of claim 1 , wherein the wafer produced using photolithography patterning proceeds through a subsequent MTJ fabrication process.

6. A method for producing pillar arrays in a wafer fabrication process, the method comprising:
performing an MTJ manufacturing process comprising:
fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer;
depositing a hard mask onto the metal stack;
selecting a manufacturing process to pattern an array of pillars on the hard mask from a plurality of manufacturing processes based on a maturity level of the MTJ manufacturing process, the plurality of manufacturing processes comprising:
a first manufacturing process that uses an electron beam to pattern a first array of pillars into the hard mask to produce a resulting pillar array, wherein the first manufacturing process is configured for a research and development phase; and
a second manufacturing process that uses photolithography to pattern a second array of pillars into the hard mask to produce the resulting pillar array, wherein the manufacturing process is configured for a high-volume production phase

performing the selected manufacturing process to produce the resulting pillar array on the hard mask.

7. The method of claim 6 , further comprising performing a reactive ion etch process to etch the hard mask to form hard mask pillars on top of the metal stack, wherein the hard mask comprises an electron beam lithography hard mask.

8. The method of claim 6 , further comprising performing reactive ion etching (REI) to etch the hard mask to form hard mask pillars on top of the metal stack, wherein the hard mask comprises a multilayer photolithography hard mask.

9. The method of claim 6 , wherein the hard mask comprises a multilayer photolithography hard mask comprising a bottom antireflective coating (BARC) layer, a first hard mask layer, and a second hard mask layer.

10. The method of claim 9 , wherein the first hard mask layer comprises tantalum nitride and the second hard mask layer comprises silicon oxide.

11. A method for manufacturing an MRAM device, the method comprising:
performing an MTJ manufacturing process comprising:
fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer;
depositing a hard mask onto the metal stack;
selecting a manufacturing process to pattern an array of pillars on the hard mask from a plurality of manufacturing processes based on a maturity level of the MTJ manufacturing process, the plurality of manufacturing processes comprising:
a first manufacturing process that uses an electron beam to pattern a first array of pillars into the electron beam lithography hard mask to produce a resulting pillar array, wherein the first manufacturing process is configured for a research and development phase; and
a second manufacturing process that uses photolithography to pattern a second array of pillars into the hard mask to produce the resulting pillar array, wherein the second manufacturing process is configured for a high-volume production phase,

performing the selected manufacturing process to produce the resulting pillar array on the hard mask; and

outputting a plurality of wafers produced via the MTJ manufacturing process.

12. The method of claim 11 , further comprising performing a reactive ion etch process to etch the hard mask to form hard mask pillars on top of the metal stack, wherein the hard mask comprises an electron beam lithography hard mask.

13. The method of claim 11 , wherein reactive ion etching (REI) etches the hard mask to form hard mask pillars on top of the metal stack, and wherein the hard mask comprises an electron beam lithography hard mask.

14. The method of claim 11 , wherein the hard mask comprises a multilayer photolithography hard mask comprising a bottom antireflective coating (BARC) layer, a first hard mask layer, and a second hard mask layer.

15. The method of claim 11 , wherein the hard mask comprises a photolithography hard mask that is over exposed with multiple dose conditions to achieve a desired critical dimension target on a completed wafer.

16. The method of claim 15 , wherein multiple REI processes are utilized to trim the photolithography hard mask to achieve the desired critical dimension target.

Assignees

• Spin Memory Inc

Inventors

• Shrivastava Prachi
• Liu Daniel
• Chin Yuan Tung

Classifications

• H01L27/222

  Electricity · mapped topic

• H01L43/02 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/01

  Manufacture or treatment · CPC title