Transistor device with gate resistor

Patent metadata

Field	Value
Publication number	US-10811531-B2
Application number	US-201916284625-A
Country	US
Kind code	B2
Filing date	Feb 25, 2019
Priority date	Feb 26, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

Disclosed is a transistor device with at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, and a gate pad arranged on top of the semiconductor body and electrically connected to the gate runner. The gate runner includes a first metal line, a second metal line on top of the first metal line, a first gate runner section, and at least one second gate runner section. The at least one second gate runner section is arranged between the first gate runner section and the gate pad. A cross sectional area of the second metal line in the at least one second gate runner section is less than 50% of the cross sectional area of the second metal line in the first gate runner section.

First claim

What is claimed is:

1. A transistor device, comprising:
at least one gate electrode;
a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body; and
a gate pad arranged on top of the semiconductor body and electrically connected to the gate runner,
wherein the gate runner comprises a first metal line, a second metal line on top of the first metal line, a first gate runner section, and at least one second gate runner section,
wherein the at least one second gate runner section is arranged between the first gate runner section and the gate pad,
wherein a cross sectional area of the second metal line in the at least one second gate runner section is less than 50% of the cross sectional area of the second metal line in the first gate runner section.

2. The transistor device of claim 1 , wherein the second metal line is omitted in the at least one second gate runner section.

3. The transistor device of claim 1 , wherein a cross sectional area of the first metal line is smaller in the at least one second gate runner section than in the first gate runner section.

4. The transistor device of claim 1 , wherein a height of the second metal line is approximately equal in the first gate runner section and the at least one second gate runner section.

5. The transistor device of claim 1 , wherein the first metal line comprises tungsten.

6. The transistor device of claim 1 , wherein the second metal line comprises an aluminum copper alloy.

7. The transistor device of claim 1 , further comprising:
a plurality of transistor cells each comprising a source region and a body region integrated in the semiconductor body,
wherein the body region is adjacent the at least one gate electrode and dielectrically insulated from the at least one gate electrode by a gate dielectric.

8. The transistor device of claim 1 , wherein the at least one gate electrode comprises a plurality of elongated gate electrodes.

9. The transistor device of claim 1 , wherein the at least one gate electrode comprises a grid-shaped gate electrode.

10. The transistor device of claim 1 , wherein the at least one gate electrode comprises a metal.

11. The transistor device of claim 10 , wherein the metal comprises tungsten.

12. The transistor device of claim 1 , further comprising:
a plurality of contact plugs electrically connecting the at least one gate electrode to the gate runner.

13. The transistor device of claim 12 , wherein the plurality of contact plugs is only connected to the first gate runner section.

14. A method, comprising:
forming a first metal layer on top of a semiconductor body, the first metal layer forming a first metal line of a gate runner and a first layer of a gate pad of a transistor device; and
forming a second metal layer on top of the first metal layer, the second metal layer forming a second metal line of the gate runner and a second layer of the gate pad,
wherein forming the second metal layer comprises forming the second metal layer such that a cross sectional area of the second metal layer in at least one second gate runner section is less than 50% of the cross sectional area of the second metal layer in a first gate runner section,
wherein the at least one second gate runner section is arranged between the first gate runner section and the gate pad.

15. The method of claim 14 , wherein forming the second metal layer such that the cross sectional area of the second metal layer in the at least one second gate runner section is less than 50% of the cross sectional area of the second metal layer in the first gate runner section comprises forming the second metal layer such that the cross sectional area of the second metal layer in the at least one second gate runner section is less than 20% of the cross sectional area of the second metal layer in the first gate runner section.

16. The method of claim 15 , wherein forming the second metal layer such that the cross sectional area of the second metal layer in the at least one second gate runner section is less than 20% of the cross sectional area of the second metal layer in the first gate runner section comprises omitting the second metal layer in the second gate runner section.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Laforet David
• Blank Oliver
• Braz Cesar Augusto
• Noebauer Gerhard
• Ouvrard Cedric

Classifications

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D64/517

  characterised by the conducting layers · CPC title