Low voltage trench metal oxide semiconductor field effect transistor

Patent metadata

Field	Value
Publication number	US-2017194316-A1
Application number	US-201615373906-A
Country	US
Kind code	A1
Filing date	Dec 9, 2016
Priority date	Dec 31, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A semiconductor device includes a substrate and a source metal formed on the substrate. A gate pad is formed on the substrate adjacent to the source metal. A gate metal is formed on the substrate and surrounds the gate pad and the source metal. A first diode is formed between the gate metal and the source metal.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a source metal formed on the substrate; a gate pad formed on the substrate adjacent to the source metal; a gate metal formed on the substrate and surrounding the gate pad and the source metal; and a diode formed between the gate metal and the source metal.

2 . The semiconductor device of claim 1 , wherein the diode is further formed between the source metal and the gate pad.

3 . The semiconductor device of claim 1 , wherein the diode comprises a first electrode connected to the source metal and a second electrode connected to the gate metal.

4 . The semiconductor device of claim 3 , wherein the diode further comprises:
a pair of first regions doped with a first conductivity type impurity; and a second region doped with a second conductivity type impurity and sandwiched between the pair of first regions.

5 . The semiconductor device of claim 1 , wherein the gate metal is connected to the gate pad.

6 . The semiconductor device of claim 1 , further comprising:
a trench formed in the substrate; and a gate electrode formed in the trench.

7 . The semiconductor device of claim 6 , further comprising a protection film formed on side and bottom surfaces of the substrate surrounding the trench,
wherein the gate electrode is formed on the protection film in the trench.

8 . The semiconductor device of claim 6 , wherein the trench comprises at least one of:
a first trench extending between a portion of the substrate underlying the source metal and a portion of the substrate underlying the gate pad; and a second trench extending between a portion of the substrate underlying the source metal and a portion of the substrate underlying the gate metal.

9 . The semiconductor device of claim 6 , wherein the trench comprises:
a cell trench formed in a portion of the substrate underlying the source metal; and an extended trench formed in the substrate and extending from the portion of the substrate underlying the source metal to a portion of the substrate underlying the gate pad or the gate metal, and wherein the gate electrode comprises:
a cell gate electrode formed in the cell trench; and
an extended gate electrode formed in the extended trench.

10 . The semiconductor device of claim 1 , further comprising a gate resistor connected between the gate pad and the gate metal.

11 . The semiconductor device of claim 1 , comprising a trench metal oxide silicon field effect transistor (MOSFET).

12 . A semiconductor device, comprising:
a substrate; a first source metal formed on the substrate; a gate pad formed on the substrate adjacent to the source metal with a first gap therebetween; a gate metal formed on the substrate and at least partially surrounding the first source metal; a second source metal formed on the substrate and surrounding the gate metal with a second gap therebetween; and a diode formed on the substrate in the second gap between the second source metal and the gate metal.

13 . The semiconductor device of claim 12 , wherein the gate metal is connected to the gate pad.

14 . The semiconductor device of claim 12 , further comprising a gate resistor coupled between the gate pad and the gate metal.

15 . The semiconductor device of claim 12 , wherein the diode comprises a first electrode connected to the second source metal and a second electrode connected to the gate metal.

16 . The semiconductor device of claim 15 , wherein the diode further comprises:
a pair of first regions doped with a first conductivity type impurity; and a second region doped with a second conductivity type impurity and sandwiched between the pair of first regions.

17 . The semiconductor device of claim 12 , further comprising:
a trench formed in the substrate; and a gate electrode formed in the trench.

18 . The semiconductor device of claim 17 , further comprising a protective film formed on side and bottom surfaces of the substrate surrounding the trench,
wherein the gate electrode is formed on the protective film.

19 . The semiconductor device of claim 12 , wherein the second source metal is connected to the first source metal.

20 . A semiconductor device, comprising:
a substrate; a source metal and a gate pad formed on the substrate and spaced apart from each other; a gate metal formed on the substrate surrounding the source metal and the gate pad, wherein the gate metal is spaced apart from the source metal with a predetermined gap therebetween; and a diode formed in the predetermined gap between the source metal and the gate metal.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Kang Soo Chang
• Kim Seung Hyun
• Lee Yong Won

Classifications

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H01L27/0255

  Electricity · mapped topic

• H01L28/20

  Electricity · mapped topic

• H01L27/0288 Primary

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic