Trench gate trench field plate vertical mosfet

Patent metadata

Field	Value
Publication number	US-10811530-B2
Application number	US-201715638707-A
Country	US
Kind code	B2
Filing date	Jun 30, 2017
Priority date	Oct 3, 2013
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

First claim

What is claimed is:

1. A vertical drain extended transistor formed in a semiconductor substrate comprising:
a plurality of regions on a surface of said semiconductor substrate, wherein each of said regions is defined by a first closed boundary and a second closed boundary spaced apart from said first closed boundary, and said first closed boundary is defined by a first trench and said second closed boundary is defined by a second trench, and comprises:
a source region of a first conductivity type formed on said surface of said semiconductor substrate, extending horizontally from said first closed boundary to said second closed boundary through an entire region between said first and said second closed boundaries and extending vertically between said first and said second trenches;
a body region of a second conductivity type formed below said source region; and
a vertically oriented drift region of said first conductivity type formed below said body region, wherein:
said first trench includes an insulating liner formed on sides and bottom of said first trench and a conductive material formed on said insulating liner and electrically connected to said source region;
said second trench includes a first gate dielectric layer formed on sides and bottom of said second trench and a first trench gate formed on said first gate dielectric layer in said second trench:
said body region contacts said first gate dielectric layer at said side of said second trench;
said vertically oriented drift region contacts to said first gate dielectric layer at said bottom of said second trench; and
said first trench is deeper than a top of said vertically oriented drift region.

2. The vertical drain extended transistor of claim 1 , wherein each of said regions is further defined by a third and a fourth closed boundaries that are spaced apart from said first and said second closed boundaries, and said third closed boundary is defined by a third trench and said fourth closed boundary is defined by a fourth trench, and
said third trench includes:
a second gate dielectric layer formed on sides and bottom of said third trench; and
a second trench gate formed on said second gate dielectric layer in said third trench,

said fourth trench includes:
a third gate dielectric layer formed on sides and bottom of said fourth trench; and
a third trench gate formed on said third gate dielectric layer in said fourth trench,

said source region extending horizontally from said first closed boundary to each of said second, said third and said forth closed boundaries through an entire region between said first closed boundary and each of said second, said third and said fourth closed boundaries and extending vertically between said first, said second, said third and said fourth trenches,
said body region further contacts said second gate dielectric layer at said side of said third trench and said third gate dielectric layer at said side of said fourth trench, and
said vertically oriented drift region further contacts to said second gate dielectric layer at said bottom of said third trench and said third gate dielectric layer at said bottom of said fourth trench.

3. The vertical drain extended transistor of claim 1 , wherein said semiconductor substrate includes an epitaxial layer, and said first trench and said second trench are formed in said epitaxial layer.

4. The vertical drain extended transistor of claim 1 , wherein said first trench is 0.5 to 1.5 microns wide.

5. The vertical drain extended transistor of claim 1 , wherein said first gate dielectric layer is comprised of silicon dioxide and aluminum oxy-nitride.

Assignees

• Texas Instruments Inc

Inventors

• Denison Marie
• Pendharkar Sameer
• Mathur Guru

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title