Transistor device with gate resistor

Patent metadata

Field	Value
Publication number	US-10811529-B2
Application number	US-201916380762-A
Country	US
Kind code	B2
Filing date	Apr 10, 2019
Priority date	Apr 11, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.

First claim

What is claimed is:

1. A transistor device, comprising:
at least one gate electrode;
a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body;
a plurality of gate pads arranged on top of the semiconductor body; and
a plurality of resistor arrangements; wherein
each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements; and
each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.

2. The transistor device of claim 1 , wherein
the gate runner has an electrical resistance; and
the electrical resistance of at least one of the plurality of resistor arrangements is greater than the electrical resistance of the gate runner.

3. The transistor device of claim 1 , wherein
each resistor arrangement comprises a first conducting layer within the semiconductor body;
the first conducting layer of each of the resistor arrangements has a first thickness in a vertical direction of the semiconductor body; and
the first thicknesses of the first conducting layers of the plurality of resistor arrangements are identical.

4. The transistor device of claim 3 , wherein
the first conducting layer of each of the resistor arrangements has a first width in a horizontal direction of the semiconductor body perpendicular to the vertical direction; and
the first widths of the first conducting layers of the plurality of resistor arrangements differ from each other.

5. The transistor device of claim 3 , wherein each resistor arrangement further comprises:
a first via configured to electrically couple the respective gate pad to the first conducting layer; and
a second via configured to electrically couple the respective first conducting layer to the gate runner.

6. The transistor device of claim 5 , further comprising:
at least one third via configured to electrically couple the gate runner to the at least one gate electrode.

7. The transistor device of claim 3 , wherein the first conducting layers comprise polysilicon.

8. The transistor device of claim 1 , wherein
each resistor arrangement comprises a first conducting layer within the semiconductor body;
the first conducting layer of each of the resistor arrangements has a first width in a horizontal direction parallel to a top surface of the semiconductor body on which the plurality of gate pads are arranged; and
the first widths of the first conducting layers of the plurality of resistor arrangements differ from each other.

9. The transistor device of claim 1 , wherein at least one of the plurality of resistor arrangements comprises a diode, a first resistor section and a second resistor section, wherein
the first resistor section and the second resistor section are coupled in series between the respective gate pad and the gate runner; and
the diode is coupled in parallel to the first resistor section between the respective gate pad and second resistor section.

10. The transistor device of claim 9 , wherein
each first resistor section has a first electrical resistance, and each second resistor section has a second electrical resistance;
when an electrical current flows through the resistor arrangement in a first direction, the diode of the respective resistor arrangement is in a conducting state, and the electrical resistance of the respective resistor arrangement is determined essentially by the second electrical resistance; and
when an electrical current flows through the resistor arrangement in a second direction, the diode of the respective resistor arrangement is in a blocking state, and the electrical resistance of the respective resistor arrangement is determined essentially by a sum of the first electrical resistance and the second electrical resistance of the respective resistor arrangement.

11. The transistor device of claim 1 , wherein the semiconductor body has a rectangular shape and each of the at least two gate pads is arranged in one corner of the semiconductor body.

12. The transistor device of claim 1 , further comprising:
a plurality of transistor cells each comprising a source region and a body region integrated in the semiconductor body,
wherein the body region is adjacent the at least one gate electrode and dielectrically insulated from the at least one gate electrode by a gate dielectric.

13. The transistor device of claim 1 , wherein the at least one gate electrode comprises a plurality of elongated gate electrodes.

14. The transistor device of claim 1 , wherein the at least one gate electrode comprises a grid shaped gate electrode.

15. A method comprising:
forming a gate runner on top of a semiconductor body;
forming a plurality of gate pads on top of the semiconductor body; and
forming a plurality of resistor arrangements in the semiconductor body; wherein
each of the plurality of resistor arrangements is formed to electrically connect one of the gate pads to the gate runner; and
each of the plurality of resistor arrangements is formed to provide a different electrical resistance between the gate runner and the respective gate pad.

16. The method of claim 15 , wherein forming a plurality of resistor arrangements in the semiconductor body further comprises:
forming a plurality of first resistor sections and a plurality of second resistor sections, wherein a first resistor section and a corresponding second resistor section are coupled in series between one of the respective gate pads and the gate runner; and
forming a plurality of diodes, wherein each of the diodes is coupled in parallel to one of the first resistor sections between the respective gate pad and second resistor section.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Riegler Andreas
• Fachmann Christian
• Fischer Bjoern
• Hirler Franz
• Mezoesi Gabor
• Weber Hans

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/143

  the built-in components being PN junction diodes · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title