Encapsulation of advanced devices using novel PECVD and ALD schemes

Patent metadata

Field	Value
Publication number	US-9812338-B2
Application number	US-201313804126-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Mar 14, 2013
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Embodiments of a multi-layer environmental barrier for a semiconductor device and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor device is formed on a semiconductor die. The semiconductor die includes a semiconductor body and a passivation structure on the semiconductor body. A multi-level environmental barrier is provided on the passivation structure. The multi-layer environmental barrier is a low-defect multi-layer dielectric film that hermetically seals the semiconductor device from the environment. In one embodiment, the multi-layer environmental barrier has a defect density of less than 10 defects per square centimeter (cm 2 ). By having a low defect density, the multi-layer environmental barrier serves as a robust barrier to the environment.

First claim

What is claimed is:

1. A semiconductor die comprising:
a semiconductor body;
a passivation structure on the semiconductor body; and
a multi-layer environmental barrier on the passivation structure, the multi-layer environmental barrier comprising three layers of different materials, wherein the multi-layer environmental barrier has a repeating structure and there are at least two repeating structures.

2. The semiconductor die of claim 1 wherein the multi-layer environmental barrier comprises multiple Plasma Enhanced Chemical Vapor Deposition (PECVD) layers.

3. The semiconductor die of claim 2 wherein the multi-layer environmental barrier has less than 10 defects per square centimeter.

4. The semiconductor die of claim 1 wherein the multi-layer environmental barrier comprises multiple Atomic Layer Deposition (ALD) layers.

5. The semiconductor die of claim 1 wherein the passivation structure comprises silicon nitride.

6. The semiconductor die of claim 1 , wherein the multi-layer environmental barrier comprises at least a silicon nitride layer and a silicon oxide layer.

7. The semiconductor die of claim 1 , wherein the multi-layer environmental barrier comprises a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

8. The semiconductor die of claim 1 wherein the semiconductor die is a High Electron Mobility Transistor.

9. The semiconductor die of claim 1 wherein the semiconductor die is a Metal Oxide Semiconductor Field Effect Transistor.

10. A method comprising:
providing a semiconductor body;
providing a passivation structure on the semiconductor body; and
providing a multi-layer environmental barrier on the passivation structure, the multi-layer environmental barrier comprising three layers of different materials, wherein the multi-layer environmental barrier has a repeating structure and there are at least two repeating structures.

11. The method of claim 10 wherein providing the multi-layer environmental barrier comprises providing multiple Plasma Enhanced Chemical Vapor Deposition (PECVD) layers.

12. The method of claim 10 wherein providing the multi-layer environmental barrier comprises providing multiple Atomic Layer Deposition (ALD) layers.

13. The method of claim 10 wherein the passivation structure comprises silicon nitride.

14. The method of claim 10 wherein the semiconductor body, the passivation structure, and the multi-layer environmental barrier form a High Electron Mobility Transistor.

15. The method of claim 10 wherein the semiconductor body, the passivation structure, and the multi-layer environmental barrier form a Metal Oxide Semiconductor Field Effect Transistor.

16. The method of claim 10 , wherein the multi-layer environmental barrier comprises a silicon nitride layer and a silicon oxide layer.

17. The method of claim 10 , wherein the multi-layer environmental barrier comprises a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

Assignees

• Cree Inc

Inventors

• Ring Zoltan
• Hagleitner Helmut
• Namishia Daniel

Classifications

• H10W74/147 Primary

  the encapsulations being multilayered · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W74/01 Primary

  Manufacture or treatment · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L21/56 Primary

  Electricity · mapped topic