Semiconductor device

Patent metadata

Field	Value
Publication number	US-10804253-B2
Application number	US-201616088735-A
Country	US
Kind code	B2
Filing date	Aug 10, 2016
Priority date	Aug 10, 2016
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

First and second circuit patterns ( 5,6 ) are provided on an insulating substrate ( 1 ). First and second semiconductor chips ( 7,8 ) are provided on the first circuit pattern ( 5 ). A relay circuit pattern ( 10 ) is provided between the first semiconductor chip ( 7 ) and the second semiconductor chip ( 8 ) on the insulating substrate ( 1 ). A wire ( 11 ) is continuously connected to the first semiconductor chip ( 7 ), the relay circuit pattern ( 10 ), the second semiconductor chip ( 8 ) and the second circuit pattern ( 6 ) which are sequentially arranged in one direction.

First claim

The invention claimed is:

1. A semiconductor device comprising:
an insulating substrate;
first and second circuit patterns provided on the insulating substrate;
first and second semiconductor chips provided on the first circuit pattern;
a relay circuit pattern provided between the first semiconductor chip and the second semiconductor chip on the insulating substrate; and
a wire continuously connected to the first semiconductor chip, the relay circuit pattern, the second semiconductor chip and the second circuit pattern which are sequentially arranged in one direction.

2. The semiconductor device according to claim 1 , wherein pluralities of each of the first and second semiconductor chips are provided, and
the relay circuit pattern is electrically connected to upper surface electrodes of the pluralities of first and second semiconductor chips to equalize potentials of the upper surface electrodes of the pluralities of first and second semiconductor chips.

3. The semiconductor device according to claim 1 , wherein the relay circuit pattern is higher in thermal conductivity than the first and second circuit patterns.

4. The semiconductor device according to claim 1 , further comprising a high thermal conductivity film which is provided on the relay circuit pattern and higher in thermal conductivity than the relay circuit pattern and the first and second circuit patterns.

5. The semiconductor device according to claim 1 , wherein thickness of the relay circuit pattern is larger than thickness of the first and second circuit patterns, and
height of an upper surface of the relay circuit pattern is not less than height of upper surfaces of the first and second semiconductor chips.

6. The semiconductor device according to claim 1 , wherein
the wire is a single wire, the first semiconductor chip is a start point of wire bonding of the single wire and the second circuit pattern is an end point of wire bonding of the single wire.

Assignees

• Mitsubishi Electric Corp

Inventors

• Hayashida Yukimasa
• Tsuda Ryo
• Date Ryutaro

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title