Dissimilar material interface having lattices

Patent metadata

Field	Value
Publication number	US-10804201-B2
Application number	US-201816236101-A
Country	US
Kind code	B2
Filing date	Dec 28, 2018
Priority date	Dec 28, 2017
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

A structure for a semiconductor device includes a dielectric layer and a metal layer. The structure also includes a plurality of unit cells. Each unit cell is formed of interconnected segments. The plurality of unit cells forms a lattice. The lattice is between the dielectric layer and the metal layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a dielectric layer;
a metal layer; and
interconnected graphene segments between the dielectric layer and the metal layer, wherein the interconnected graphene segments form a hollow tube.

2. The semiconductor device of claim 1 , wherein the dielectric layer and the metal layer are at least part of a back-end-of-line (BEOL) portion of a semiconductor device.

3. The semiconductor device of claim 1 , wherein the dielectric layer comprises at least one material selected from the group consisting of SiO2, Al2O3, ZrO2, SiN, Tetraethyl Orthosilicate (TEOS), Polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), and combinations thereof, and the metal layer comprises at least one element selected from the group consisting of W, Cu, Al, Ni, Pd, Au, Ag, and combinations thereof.

4. The semiconductor device of claim 1 , wherein the metal layer has a coefficient of thermal expansion that is different than a coefficient of thermal expansion of the dielectric layer.

5. The semiconductor device of claim 1 , wherein the hollow tube is filled with a non-conducting material.

6. A structure for a semiconductor device, the structure comprising:
a dielectric layer;
a metal-filled via; and
a plurality of unit cells, wherein each unit cell is formed of interconnected segments, and wherein the plurality of unit cells forms a lattice;
wherein the lattice contacts the dielectric layer and the metal-filled via.

7. The structure of claim 6 , wherein the dielectric layer and the metal-filled via are at least part of a back-end-of-line (BEOL) portion of a semiconductor device.

8. The structure of claim 6 , wherein the dielectric layer comprises at least one material selected from the group consisting of SiO2, Al2O3, ZrO2, SiN, Tetraethyl Orthosilicate (TEOS), Polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), and combinations thereof, and the metal-filled via comprises at least one element selected from the group consisting of W, Cu, Al, Ni, Pd, Au, Ag, and combinations thereof.

9. The structure of claim 6 , wherein the metal-filled via has a coefficient of thermal expansion that is different than a coefficient of thermal expansion of the dielectric layer.

10. The structure of claim 6 , wherein each of the interconnected segments is a hollow tube.

11. The structure of claim 6 , wherein each of the interconnected segments is a tube filled with a non-conducting material.

12. A structure for a back-end-of-line (BEOL) portion of an integrated circuit package, the structure comprising:
a dielectric layer;
a metal layer;
a metal-filled via connected to the metal layer; and
a plurality of lattices, each lattice comprises a plurality of unit cells, wherein each unit cell is formed of interconnected segments;
wherein a first lattice of the plurality of lattices is between the dielectric layer and the metal layer; and
wherein a second lattice of the plurality of lattices is between the dielectric layer and the metal-filled via.

13. The structure of claim 12 , wherein the metal layer and the metal-filled via have coefficients of thermal expansion that are different than a coefficient of thermal expansion of the dielectric layer.

14. The structure of claim 12 , wherein each of the interconnected segments is a hollow tube.

15. The structure of claim 12 , wherein each of the interconnected segments is a tube filled with a non-conducting material.

16. A method of forming a structure for a back-end-of-line (BEOL) portion of an integrated circuit package, the method comprising:
forming a dielectric layer;
forming a metal layer;
forming a metal-filled via connected to the metal layer; and
forming a plurality of lattices between the dielectric layer and the metal layer, and between the dielectric layer and the metal-filled via, each lattice is formed by:
photo-initiating polymerization of a monomer in a pattern of unit cells to form a polymer lattice, wherein each unit cell is formed of interconnected segments;

removing the unpolymerized monomer;
coating the polymer lattice with a metal;
removing the polymer lattice to leave a metal lattice;
depositing graphitic carbon on the metal lattice;
converting the graphitic carbon to graphene or graphitic tubes; and
removing the metal lattice.

17. The method of claim 16 , wherein the metal layer and the metal-filled via have coefficients of thermal expansion that are different than a coefficient of thermal expansion of the dielectric layer.

18. The method of claim 16 , wherein each of the interconnected segments is a hollow tube.

19. The method of claim 16 , wherein each of the interconnected segments is a tube filled with a non-conducting material.

Assignees

• Texas Instruments Inc

Inventors

• Venugopal Archana
• Cook Benjamin Stassen
• Dadvand Nazila
• Colombo Luigi

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/4462

  Carbon or carbon-containing materials, e.g. graphene · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/094

  by transforming insulators into conductors · CPC title

• H10W20/044

  for electroless plating · CPC title