Disaggregation of SOC architecture

Patent metadata

Field	Value
Publication number	US-10803548-B2
Application number	US-201916355377-A
Country	US
Kind code	B2
Filing date	Mar 15, 2019
Priority date	Mar 15, 2019
Publication date	Oct 13, 2020
Grant date	Oct 13, 2020

Abstract

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

First claim

What is claimed is:

1. A general-purpose graphics processor comprising:
a three-dimensional (3D) package assembly including multiple packaged chiplets, the package assembly including:
a base die including an interconnect fabric and a silicon interconnect bridge, the interconnect fabric and the silicon interconnect bridge integrated within the base die;
one or more distinctly packaged chiplets coupled with the base die via one or more interconnect structures, the one or more interconnect structures to enable electrical communication between the one or more distinctly packaged chiplets and hardware logic within the base die wherein the one or more distinctly packaged chiplets include:
a first chiplet coupled with the base die via a first interconnect structure, wherein the first chiplet includes a first fabric interconnect node and functional units configured to perform general-purpose graphics processing operations, the first fabric interconnect node to enable communication with the interconnect fabric within the base die; and
a second chiplet coupled with the base die via a second interconnect structure, wherein the second chiplet includes memory cells associated with a memory device and the second chiplet is coupled with the first chiplet via the silicon interconnect bridge.

2. The general-purpose graphics processor as in claim 1 , wherein the first chiplet includes an interconnect buffer to store data received via the first fabric interconnect node.

3. The general-purpose graphics processor as in claim 2 , wherein the first chiplet includes an interconnect cache coupled with the first fabric interconnect node, the interconnect cache to cache data transmitted and received via the first fabric interconnect node.

4. The general-purpose graphics processor as in claim 2 , additionally comprising a third chiplet coupled with the base die via a third interconnect structure.

5. The general-purpose graphics processor as in claim 4 , wherein the third chiplet includes a network processor and a physical network interface.

6. The general-purpose graphics processor as in claim 4 , wherein the third chiplet includes functional units configured to perform media encode or decode operations.

7. The general-purpose graphics processor as in claim 4 , wherein the third chiplet includes a second fabric interconnect node to enable communication with the interconnect fabric within the base die.

8. The general-purpose graphics processor as in claim 4 , wherein the memory device associated with the memory cells of the second chiplet is a cache memory device and the silicon interconnect bridge includes an I/O layer and a protocol layer.

9. The general-purpose graphics processor as in claim 4 , wherein the first chiplet, second chiplet, and third chiplet are independently power gated.

10. The general-purpose graphics processor as in claim 1 , wherein the base die includes a cache memory and the cache memory is connected to the interconnect fabric.

11. The general-purpose graphics processor as in claim 10 , wherein the cache memory is configured as a processor-wide cache.

12. A data processing system comprising:
a three-dimensional (3D) package assembly including multiple packaged chiplets, the package assembly including:
a general-purpose graphics processor comprising a base die including an interconnect fabric and a silicon interconnect bridge, the interconnect fabric and the silicon interconnect bridge integrated within the base die and multiple distinctly packaged chiplets coupled with the base die via multiple interconnect structures, the multiple interconnect structures to enable electrical communication between the multiple chiplets and the interconnect fabric,
wherein the multiple distinctly packaged chiplets include a first chiplet including a first fabric interconnect node and functional units configured to perform general-purpose graphics processing operations and a second chiplet including a second fabric interconnect node and functional units configured to perform media encode or decode operations,
wherein the interconnect fabric is to receive a message or signal from the first fabric interface node and relay the message or signal to the second fabric interface node, and
wherein the silicon interconnect bridge is to relay electrical signals from the first chiplet to a third chiplet of the multiple chiplets, the third chiplet including memory cells of a memory device.

13. The data processing system as in claim 12 , wherein the interconnect fabric is to transmit messages or signals via multiple virtual channels over multiple physical links of the interconnect fabric.

14. The data processing system as in claim 13 , wherein the interconnect fabric is to transmit data for a single virtual channel across multiple physical links of the interconnect fabric.

15. The data processing system as in claim 13 , wherein the interconnect fabric is to transmit data for multiple virtual channels across a single physical link of the interconnect fabric.

16. The data processing system as in claim 13 , wherein a physical link of the multiple physical links is power gated when the physical link is idle.

17. A method comprising:
via hardware logic of a processor including a three-dimensional (3D) package assembly having multiple distinctly packaged chiplets coupled with a base die:
generating data at a first functional unit within a chiplet of the multiple distinctly packaged chiplets, wherein the base die includes a first integrated circuit and the chiplet includes a second, distinctly packaged, integrated circuit;
caching the data in an interconnect cache within the chiplet, the interconnect cache coupled with a first fabric interface node;
transmitting the data to an interconnect fabric via the first fabric interface node;
transporting the data across multiple clock domains within the processor, the data transported from a first transport layer of the interconnect fabric to a second transport layer of the interconnect fabric;
receiving the data at a second fabric interface node;
transmitting the data to a second functional unit of the first integrated circuit; and
performing an operation at the second functional unit based on received data.

18. The method as in claim 17 , additionally comprising associating the data with a virtual channel of the interconnect fabric and forwarding or switching the data based on the virtual channel.

19. The method as in claim 18 , additionally comprising:
diverging the virtual channel at the first fabric interface node;
transporting data of the virtual channel across the multiple clock domains using multiple physical links; and
converging the virtual channel at the second fabric interface node.

20. The method as in claim 18 , wherein the virtual channel is a first virtual channel and the method additionally comprises:
converging the first virtual channel at the first fabric interface node with a second virtual channel;
transporting the first virtual channel and the second virtual channel across the multiple clock domains using a single physical link; and
diverging the first virtual channel at the second virtual channel at the second fabric interface node.

Assignees

• Intel Corp

Inventors

• Matam Naveen
• Cheney Lance
• Finley Eric
• George Varghese
• Jahagirdar Sanjeev
• Koker Altug
• Mastronarde Josh
• Rajwani Iqbal
• Striramassarma Lakshminarayanan
• Teshome Melaku
• Vemulapalli Vikranth
• Xavier Binoj

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• G06F13/18

  based on priority control (G06F13/1605 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title