Imaging device

Patent metadata

Field	Value
Publication number	US-10797100-B2
Application number	US-201916295538-A
Country	US
Kind code	B2
Filing date	Mar 7, 2019
Priority date	Sep 12, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

An imaging device includes a semiconductor substrate, pixels, a charge detector, charge storage portions, an output gate portion and a shift gate portion. The pixels and the charge detector are provided in the semiconductor substrate. The charge storage portions are provided on the charge detector side of the pixels, and linked to the pixels. The output gate portion is positioned between the charge detector and the charge storage portions, and includes charge transfer channels extending in a radial configuration in directions from the charge detector toward the pixels. The shift gate portion is positioned between one charge storage portion and one charge transfer channel. The shift gate portion includes a gate electrode provided on the semiconductor substrate. A planar configuration of the gate electrode has a side orthogonal to the extending direction of the one charge transfer channels, the side being most proximal to the one charge transfer channel.

First claim

What is claimed is:

1. An imaging device, comprising:
a semiconductor substrate;
a plurality of pixels provided in the semiconductor substrate and arranged in a first direction along a front surface of the semiconductor substrate;
a charge detector provided in the semiconductor substrate, the charge detector being provided at a position separated from a column of the plurality of pixels in a second direction orthogonal to the first direction;
a plurality of charge storage portions provided on the charge detector side of the column of the plurality of pixels, the plurality of charge storage portions being linked respectively to the plurality of pixels via charge transfer portions;
an output gate portion positioned between the charge detector and the plurality of charge storage portions, the output gate portion including a plurality of charge transfer channels extending in a radial configuration in directions from the charge detector toward the column of the plurality of pixels; and
a shift gate portion positioned between one of the plurality of charge storage portions and a charge transfer channel of the plurality of charge transfer channels, the charge transfer channel extending in a third direction crossing the first direction and the second direction,
the shift gate portion including a gate electrode provided on the semiconductor substrate, a planar configuration of the gate electrode having a side orthogonal to the third direction, the side being most proximal to the charge transfer channel extending in the third direction.

2. The device according to claim 1 , wherein
the shift gate portions is provided in a plurality, and
the plurality of charge transfer channels are provided with substantially the same distances from the plurality of shift gate portions to the charge detector.

3. The device according to claim 1 , wherein
the shift gate portion is provided a plurality, and
the plurality of charge transfer channels are provided to link the charge detector and the plurality of shift gate portions, respectively.

4. The device according to claim 1 , wherein
the output gate portion further includes an output gate electrode provided on the plurality of charge transfer channels, and
the shift gate portion is provided in a plurality, the gate electrodes of the shift gate portions being arranged along an outer edge of the output gate electrode.

5. The device according to claim 1 , wherein
the shift gate portion is provided in a plurality, the plurality of shift gate portions including a first shift gate portion and a second shift gate portion,
the first shift gate portion is provided at a position with a first distance along the second direction from the column of the plurality of pixels to the first shift gate portion, the first distance being shorter than a second distance along the second direction from the column of the plurality of pixels to the charge detector, and
the second shift gate portion is provided at a position with a third distance along the second direction from the column of the plurality of pixels to the second shift gate portion, the third distance being longer than the second distance.

6. The device according to claim 5 , wherein the charge transfer channels including other charge transfer channel linking the second shift gate portion and the charge detector, the other charge transfer channel including a branch to other one of the plurality of shift gate portions.

7. The device according to claim 6 , wherein the other charge transfer channel has a first transfer distance from the second shift gate portion to the charge detector and a second transfer distance from the other one of the plurality of shift gate portions to the charge detector, the first distance and the second distance being defined along the charge transfer channel, the second distance being same as the first distance.

8. The device according to claim 1 , wherein the shift gate portions provide timing control of charge transfer from the plurality of charge storage portions to the charge detector.

9. The device according to claim 1 , further comprising:
a charge discharging portion provided proximally to the charge detector; and
a reset gate provides timing control of charge discharging from the charge detector to the charge discharging portion.

10. The device according to claim 8 , wherein a signal voltage applied to the reset gate is applied synchronously with a signal voltage applied to the gate electrode of the shift gate portion.

11. An imaging device, comprising:
a semiconductor substrate;
a plurality of pixels provided in the semiconductor substrate and arranged in a first direction along a front surface of the semiconductor substrate;
a charge detector provided in the semiconductor substrate and provided at a position separated from a column of the plurality of pixels in a second direction orthogonal to the first direction;
a plurality of charge storage portions provided on the charge detector side of the column of the plurality of pixels, the plurality of charge storage portions linked respectively to the plurality of pixels via charge transfer portions;
an output gate portion positioned between the charge detector and the plurality of charge storage portions, the output gate portion including a plurality of charge transfer channels extending in a radial configuration in directions from the charge detector toward the column of the plurality of pixels; and
a shift gate portion positioned between one of the plurality of charge storage portions and one charge transfer channel of the plurality of charge transfer channels, the shift gate portion including a gate electrode provided on the semiconductor substrate,
a planar configuration of the gate electrode having a corner most proximal to an end of the one charge transfer channel, the one charge transfer channel being connected to the shift gate portion at a vicinity of the corner.

12. The device according to claim 11 , wherein
the output gate portion further includes an output gate electrode provided on the plurality of charge transfer channels, and
the output gate electrode has a recess at an outer edge of the output gate electrode, the recess corresponding to the corner of the gate electrode.

13. The device according to claim 11 , wherein
the shift gate portion is provided in a plurality, and
the plurality of charge transfer channels is provided with substantially the same distances from the plurality of shift gate portions to the charge detector.

14. The device according to claim 11 , wherein
the shift gate portion is provided in a plurality, and
the plurality of charge transfer channels is provided to link the charge detector and the plurality of shift gate portions, respectively.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Inobe Ryuta

Classifications

• H04N23/54 Primary

  Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils · CPC title

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H10F39/152

  One-dimensional array CCD image sensors · CPC title

• H10F39/80373

  characterised by the gate of the transistor · CPC title

• H10F39/8037

  the integrated elements comprising a transistor · CPC title