Solid-state image-capturing element and electronic device

Patent metadata

Field	Value
Publication number	US-10797097-B2
Application number	US-201916507663-A
Country	US
Kind code	B2
Filing date	Jul 10, 2019
Priority date	Mar 31, 2015
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.

First claim

The invention claimed is:

1. A light detecting device, comprising:
a floating diffusion;
a floating diffusion wiring connected to the floating diffusion;
a first region of an insulating layer; and
a first hollow region,
wherein the floating diffusion wiring, the first region of the insulating layer, and the first hollow region are in this order in a specific direction.

2. The light detecting device according to claim 1 , wherein the specific direction is a horizontal direction.

3. The light detecting device according to claim 1 , wherein the specific direction is a vertical direction.

4. The light detecting device according to claim 1 , further comprising:
a wiring other than the floating diffusion wiring,
wherein the floating diffusion wiring, the first region of the insulating layer, the first hollow region, a second region of the insulating layer, and the wiring are in this order in a horizontal direction.

5. The light detecting device according to claim 1 , further comprising:
a transfer transistor; and
a TRG wiring connected to the transfer transistor,
wherein a second hollow region is between the floating diffusion wiring and the TRG wiring.

6. The light detecting device according to claim 1 , further comprising
a vertical signal line,
wherein at least a part of a surrounding of the vertical signal line is a third hollow region.

7. The light detecting device according to claim 1 , wherein the floating diffusion wiring is one of a plurality of floating diffusion wirings connected individually to a plurality of floating diffusions.

8. The light detecting device according to claim 1 , further comprising a plurality of first hollow regions including the first hollow region, wherein a number of the plurality of first hollow regions is greater than or equal to two.

9. The light detecting device according to claim 1 , further comprising an insulating film in a fourth region other than the first hollow region, the floating diffusion wiring, and a wiring other than the floating diffusion wiring.

10. The light detecting device according to claim 9 , wherein a first material of the insulating film formed around an upper part of the first hollow region is different from a second material of the insulating film formed around a lower part of the first hollow region.

11. The light detecting device according to claim 10 , wherein a size of the lower part of the first hollow region is larger than a size of the upper part of the first hollow region.

12. The light detecting device according to claim 11 , further comprising a plurality of first hollow regions including the first hollow region, wherein
a number of the plurality of first hollow regions is greater than or equal to two, and
lower parts of the plurality of first hollow regions are connected together and upper parts of the plurality of first hollow regions are connected together.

13. The light detecting device according to claim 1 , wherein at least a part of a fourth region between the floating diffusion wiring and a semiconductor substrate in contact with the floating diffusion wiring is the first hollow region.

14. The light detecting device according to claim 1 , further comprising:
a first semiconductor substrate on which the floating diffusion wiring, a wiring other than the floating diffusion wiring, and a wiring layer in which the first hollow region is formed are stacked;
a second semiconductor substrate bonded to the first semiconductor substrate; and
a connection section configured to electrically connect the first semiconductor substrate to the second semiconductor substrate,
wherein the first hollow region is formed around the connection section of the wiring layer.

15. The light detecting device according to claim 14 , wherein the first hollow region formed around the connection section of the wiring layer pierces through the first semiconductor substrate.

16. An electronic device, comprising:
a light detecting element, comprising:
a floating diffusion;
a floating diffusion wiring connected to the floating diffusion;
a first region of an insulating layer; and
a first hollow region,
wherein the floating diffusion wiring, the first region of the insulating layer, and the first hollow region are in this order in a specific direction.

17. A light detecting device, comprising:
a floating diffusion;
a floating diffusion wiring connected to the floating diffusion;
a wiring other than the floating diffusion wiring; and
a hollow region,
wherein the floating diffusion wiring, and the hollow region, and the wiring are in this order in a specific direction.

18. The light detecting device according to claim 17 , wherein the specific direction is a horizontal direction.

19. The light detecting device according to claim 17 , wherein the specific direction is a vertical direction.

20. The light detecting device according to claim 17 ,
wherein the floating diffusion wiring, a first region of an insulating layer, the hollow region, a second region of the insulating layer, and the wiring are disposed in this order in a horizontal direction.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Tanaka Yusuke
• Nagano Takashi
• Wakano Toshifumi
• Matsunuma Takeshi

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title