Method for fabricating electronic package

Patent metadata

Field	Value
Publication number	US-10796970-B2
Application number	US-201816166811-A
Country	US
Kind code	B2
Filing date	Oct 22, 2018
Priority date	Jul 3, 2015
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.

First claim

What is claimed is:

1. A method for fabricating an electronic package, comprising:
providing a first circuit structure having opposite first and second surfaces, wherein the first circuit structure has at least a first redistribution layer;
disposing a plurality of first electronic elements on the first surface of the first circuit structure;
disposing at least a first conductive element on the first surface of the first circuit structure;
forming a first encapsulant on the first surface of the first circuit structure to encapsulate the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant;
forming a first metal layer on the first encapsulant, wherein the first metal layer is a circuit layer and in direct contact with the first conductive element and the first encapsulant;
forming a second circuit structure on the second surface of the first circuit structure, wherein the second circuit structure is in direct contact with the second surface of the first circuit structure and has at least a second redistribution layer;
disposing a plurality of second electronic elements on the second circuit structure; and
forming a second encapsulant on the second circuit structure to encapsulate the second electronic elements.

2. The method of claim 1 , further comprising:
disposing at least a second conductive element on the second circuit structure; and
forming the second encapsulant on the second circuit structure to encapsulate the second electronic elements and the second conductive element, with a portion of the second conductive element exposed from the second encapsulant.

3. The method of claim 2 , further comprising forming a second metal layer on the second encapsulant and in contact with the second conductive element.

4. The method of claim 2 , further comprising forming a conductor wall on at least one of the second circuit structure and the first surface of the first circuit structure.

5. The method of claim 4 , further comprising encapsulating the conductor wall on the second circuit structure with the second encapsulant, wherein a portion of the conductor wall on the second circuit structure is exposed from the second encapsulant.

6. The method of claim 4 , further comprising encapsulating the conductor wall on the first surface of the first circuit structure with the first encapsulant, wherein a portion of the conductor wall on the first surface of the first circuit structure is exposed from the first encapsulant.

7. The method of claim 1 , wherein a portion of the second circuit structure is exposed from the second encapsulant.

8. The method of claim 1 , wherein a portion of the first circuit structure is exposed from the first encapsulant.

9. The method of claim 2 , further comprising performing an electrical test on the first electronic elements, the first conductive element, the first circuit structure and the second circuit structure.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi
• Lu Chang-Lun

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title