Memory system, storage device, and method for controlling memory system

Patent metadata

Field	Value
Publication number	US-10031865-B2
Application number	US-201515527374-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Nov 26, 2014
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

First claim

The invention claimed is:

1. A memory system, comprising:
a read processing unit configured to perform a read process, for reading read data from each of a plurality of memory cells, based on a first threshold;
an error detection unit configured to detect presence or absence of an error, from a number of errors, in the read data, and to specify memory cells in which the error is present among the plurality of memory cells;
a re-read processing unit configured to perform a re-read process for reading data, as re-read data, from the specified memory cells, based on a second threshold different from the first threshold; and
a refresh processing unit configured to rewrite, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

2. The memory system according to claim 1 , further comprising:
a refresh control unit configured to allow the re-read unit to perform the re-read process for a memory cell, in which the error having a predetermined pattern has occurred, among the specified memory cells.

3. The memory system according to claim 2 , further comprising:
an address holding unit configured to hold a number of addresses allocated to the specified memory cells in which the error is present,
wherein, when a predetermined condition has been satisfied, the refresh control unit reads one of the number of the held addresses, designates the address, and allows the read processing unit to perform the read process.

4. The memory system according to claim 3 , wherein the predetermined condition is that the number of the held addresses exceed a predetermined number.

5. The memory system according to claim 3 , wherein the predetermined condition is that the refresh control unit have received a refresh command instructing that the refresh process be performed.

6. The memory system according to claim 2 , wherein the plurality of memory cells are divided into a plurality of sections, one of a plurality of addresses being allocated to each of the plurality of sections, and
when a refresh mode for performing the refresh process has been set, the refresh control unit sequentially designates each of the plurality of addresses and allows the read processing unit to perform the read process.

7. The memory system according to claim 6 , wherein, when the number of the errors having the predetermined pattern exceeds an allowable value, the refresh control unit allows the re-read unit to perform the re-read process for a memory cell, in which the error having the predetermined pattern has occurred, among the specified memory cells.

8. The memory system according to claim 1 , wherein each of the plurality of memory cells holds data including a plurality of bits, and
each of the first and second thresholds includes a plurality of thresholds.

9. The memory system according to claim 1 , wherein
a characteristic value of the specified memory cells changes in a specific direction each time data is read, and
the second threshold is a value obtained by changing the first threshold in the specific direction.

10. A storage device, comprising:
a plurality of memory cells;
a read processing unit configured to perform a read process, for reading read data from each of the plurality of memory cells, based on a first threshold;
a re-read processing unit configured to perform a re-read process, for reading data, as re-read data, from each of memory cells having an error in the read data, based on a second threshold different from the first threshold; and
a refresh processing unit configured to rewrite, for a memory cell of which the re-read data has a different value from the read data among the memory cells which have an error in the read data, data with the re-read data as a refresh process.

11. A method for controlling a memory system, the method comprising:
a read processing process of allowing a read processing unit to perform a read process, for reading read data from each of a plurality of memory cells, based on a first threshold;
an error detection process of allowing an error detection unit to detect presence or absence of an error in the read data and to specify memory cells in which the error is present among the specified memory cells;
a re-read processing process of allowing a re-read processing unit to perform a re-read process for reading data, as re-read data, from the specified memory cells, based on a second threshold different from the first threshold; and
a refresh processing process of allowing a refresh processing unit to rewrite, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

Assignees

• Sony Corp

Inventors

• Terada Haruhiko
• Sakai Lui
• Okubo Hideaki
• Tsutsui Keiichi

Classifications

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C11/5685

  using storage elements comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G06F11/22

  Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing · CPC title