Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems

Patent metadata

Field	Value
Publication number	US-10796744-B2
Application number	US-201916438057-A
Country	US
Kind code	B2
Filing date	Jun 11, 2019
Priority date	Feb 15, 2010
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

First claim

The invention claimed is:

1. A memory array comprising:
a plurality of memory cells individually comprising a first electrode and a second electrode;
a plurality of bit lines coupled with the first electrodes of respective ones of the memory cells;
a plurality of word lines coupled with the second electrodes of respective ones of the memory cells; and
wherein the memory cells further individually comprise:
semiconductive material comprising a plurality of mobile dopants;
wherein the first and second electrodes of the individual memory cell are adjacent to the semiconductive material;
wherein the semiconductive material is configured to permit the mobile dopants to move to different locations within the semiconductive material to provide the individual memory cell with different capacitances corresponding to different programmed states of the individual memory cell at different moments in time; and
wherein the semiconductive material is configured to permit at least some of the mobile dopants to move from locations adjacent to one of the first and second electrodes of the individual memory cell when the individual memory cell is in one of the programmed states to locations which are spaced from the one of the first and second electrodes of the individual memory cell to provide the individual memory cell in another of the programmed states, wherein the individual memory cell has an increased capacitance in the another programmed state compared with the one programmed state.

2. The memory array of claim 1 wherein the semiconductive material of the individual memory cell has a region which is substantially devoid of the mobile dopants when the individual memory cell is in the one programmed state.

3. The memory array of claim 2 wherein the at least some of the mobile dopants move into the region during a change of the individual memory cell from the one programmed state to the another programmed state.

4. The memory array of claim 1 wherein the first and second electrodes of the individual memory cell are positioned opposite to one another about the semiconductive material of the individual memory cell.

5. The memory array of claim 4 wherein the semiconductive material of the individual memory cell is configured to permit the at least some of the mobile dopants to move as a result of an application of a voltage potential across the first and second electrodes of the individual memory cell.

6. The memory array of claim 4 wherein the mobile dopants are positioned at different locations throughout substantially an entirety of the semiconductive material of the individual memory cell between the first and second electrodes of the individual memory cell when the individual memory cell is in the another programmed state.

7. The memory array of claim 1 wherein the memory cells individually comprise barrier material adjacent to another of the first and second electrodes of the individual memory cell, and wherein the barrier material of the individual memory cell is impervious to movement of the mobile dopants.

8. The memory array of claim 1 wherein the one of the first and second electrodes of the individual memory cell physically contacts the semiconductive material of the individual memory cell.

9. A memory array comprising:
a plurality of memory cells individually comprising a first electrode and a second electrode;
a plurality of bit lines coupled with the first electrodes of respective ones of the memory cells;
a plurality of word lines coupled with the second electrodes of respective ones of the memory cells; and
wherein the memory cells further individually comprise:
semiconductive material comprising a plurality of mobile dopants;
wherein the first and second electrodes of the individual memory cell are adjacent to the semiconductive material;
wherein the semiconductive material is configured to permit at least some of the mobile dopants to move to different locations within the semiconductive material to provide the individual memory cell with different capacitances corresponding to different programmed states of the individual memory cell at different moments in time; and
wherein at least some of the mobile dopants are located adjacent to one of the first and second electrodes when the individual memory cell is in the different programmed states.

10. The memory array of claim 9 wherein the semiconductive material of the individual memory cell has a region which is substantially devoid of the mobile dopants when the individual memory cell is in one of the programmed states.

11. The memory array of claim 10 wherein others of the mobile dopants move into the region during a change of the individual memory cell from the one programmed state to another of the programmed states.

12. The memory array of claim 9 wherein the first and second electrodes are positioned opposite to one another about the semiconductive material of the individual memory cell.

13. The memory array of claim 12 wherein the semiconductive material of the individual memory cell is configured to permit others of the mobile dopants to move as a result of an application of a voltage potential across the first and second electrodes.

14. The memory array of claim 12 wherein the mobile dopants are positioned at different locations throughout substantially an entirety of the semiconductive material of the individual memory cell between the first and second electrodes of the individual memory cell when the individual memory cell is in one of the programmed states.

15. The memory array of claim 9 wherein the memory cells individually comprise barrier material adjacent to another of the first and second electrodes of the individual memory cell, and wherein the barrier material of the individual memory cell is impervious to movement of the mobile dopants.

16. The memory array of claim 9 wherein the one of the first and second electrodes physically contacts the semiconductive material of the individual memory cell.

Assignees

• Micron Technology Inc

Inventors

• Meade Roy E

Classifications

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H10B41/00

  Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates · CPC title

• G11C11/24 Primary

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• G11C7/00 Primary

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title