Dynamic adjustment of memory cell digit line capacitance

Patent metadata

Field	Value
Publication number	US-10796743-B2
Application number	US-201816184492-A
Country	US
Kind code	B2
Filing date	Nov 8, 2018
Priority date	Apr 11, 2016
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

First claim

What is claimed is:

1. A method, comprising:
coupling a first digit line of a first memory cell with a second digit line of a second memory cell;
applying a voltage to a plate line of the first memory cell during a period of time that the first digit line and the second digit line are coupled; and
isolating the first digit line from the second digit line based at least in part on applying the voltage to the plate line of the first memory cell.

2. The method of claim 1 , further comprising:
activating a first switching component coupled with the first memory cell and the first digit line after coupling the first digit line with the second digit line; and
activating a sense component coupled with the first memory cell after isolating the first digit line from the second digit line.

3. The method of claim 1 , further comprising:
initializing the first digit line and the second digit line to a same voltage before coupling the first digit line with the second digit line.

4. The method of claim 3 , wherein initializing the first digit line and the second digit line comprises:
activating a first switching component coupled with the first digit line and a first ground reference; and
activating a second switching component coupled with the second digit line and a second ground reference.

5. The method of claim 1 , further comprising:
identifying a logic state of the first memory cell based at least in part on isolating the first digit line from the second digit line, wherein the logic state of the first memory cell is based at least in part on a second voltage associated with a reference memory cell.

6. The method of claim 1 , further comprising:
identifying a second voltage of the first digit line based at least in part on applying the voltage to the first digit line, wherein isolating the first digit line from the second digit line is based at least in part on the second voltage.

7. The method of claim 1 , wherein coupling the first digit line with the second digit line comprises:
shorting the first digit line and the second digit line.

8. A method, comprising:
coupling a first access line of a first memory cell with a second access line of a second memory cell;
selecting the first memory cell based at least in part on coupling the first access line with the second access line;
applying a voltage to the first access line of the first memory cell after coupling the first access line with the second access line, wherein applying the voltage to the first access line is based at least in part on selecting the first memory cell, and wherein the second memory cell comprises a reference memory cell; and
isolating the first access line from the second access line based at least in part on applying the voltage to the first access line of the first memory cell.

9. An apparatus, comprising:
a first memory cell coupled with a first digit line;
a second memory cell coupled with a second digit line; and
a memory controller coupled with the first memory cell, wherein the memory controller is operable to cause the apparatus to:
couple the first digit line of the first memory cell with the second digit line of the second memory cell;
apply a voltage to a plate line of the first memory cell during a period of time that the first digit line and the second digit line are coupled; and
isolate the first digit line from the second digit line based at least in part on applying the voltage to the plate line of the first memory cell.

10. The apparatus of claim 9 , wherein the memory controller is operable to cause the apparatus to:
activate a first switching component coupled with the first memory cell and the first digit line after coupling the first digit line with the second digit line; and
activating a sense component coupled with the first memory cell after isolating the first digit line from the second digit line.

11. The apparatus of claim 9 , wherein the memory controller is operable to cause the apparatus to:
initialize the first digit line and the second digit line to a same voltage before coupling the first digit line with the second digit line.

12. The apparatus of claim 11 , wherein the memory controller is operable to cause the apparatus to initialize the first digit line and the second digit line by being operable to cause the apparatus to:
activate a switching component coupled with the first digit line and a first ground reference; and
activate a second switching component coupled with the second digit line and a second ground reference.

13. The apparatus of claim 9 , wherein the second memory cell is coupled with the second digit line by a switching component that is configured to be deactivated.

14. An apparatus comprising:
a first memory cell coupled with a first access line;
a second memory cell coupled with a second access line; and
a memory controller coupled with the first memory cell, wherein the memory controller is operable to cause the apparatus to;
couple the first access line of the first memory cell with the second access line of the second memory cell;
apply a voltage to the first access line of the first memory cell after coupling the first access line with the second access line;
identify a second voltage of the first access line based at least in part on applying the voltage to the first access line;
deactivate a switching component coupled with the first access line and the second access line based at least in part on the second voltage; and
isolate the first access line from the second access line based at least in part on applying the voltage to the first access line of the first memory cell and deactivating the switching component.

15. The apparatus of claim 14 , wherein the memory controller is operable to:
determine a logic state of the first memory cell based at least in part on deactivating the switching component coupled with the first access line and the second access line.

16. An apparatus, comprising:
a first memory cell coupled with a first access line;
a second memory cell coupled with a second access line that is coupled with the first access line;
a switching component coupled with the first access line and the second access line; and
a memory controller operable to cause the apparatus to:
activate the switching component to couple the first access line with the second access line;
apply a voltage to a third access line of the first memory cell during a period of time the switching component couples the first access line with the second access line; and
deactivate the switching component to isolate the first access line from the second access line based at least in part on applying the voltage to the third access line of the first memory cell.

17. The apparatus of claim 16 , further comprising:
a sense component coupled with the first access line, wherein the sense component is configured to determine a logic state of the first memory cell based at least in part on a reference value stored in the second memory cell.

18. An apparatus, comprising:
a first memory cell coupled with a first access line;
a second memory cell coupled with a second access line that is coupled with the first access line;
a switching component coupled with the first access line and the second access line, wherein the switching component is configured to short the first access line with the second access line upon being activated; and
a selection component coupled with the first access line and the second access line and configured isolate the first memory cell from the second memory cell

Assignees

• Micron Technology Inc

Inventors

• Kawamura Christopher
• Ingalls Charles
• Derner Scott

Classifications

• G11C11/2255

  Bit-line or column circuits · CPC title

• G11C11/2259

  Cell access · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/2273 Primary

  Reading or sensing circuits or methods · CPC title