Computer implemented system and method for generating a layout of a cell defining a circuit component

Patent metadata

Field	Value
Publication number	US-10796053-B2
Application number	US-201816140461-A
Country	US
Kind code	B2
Filing date	Sep 24, 2018
Priority date	Nov 19, 2013
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

First claim

We claim:

1. A method comprising:
identifying a first cell layout for a first cell architecture;
identifying a second cell layout for a second cell architecture that is different than the first cell layout of the first cell architecture;
identifying one or more cut lines relative to the first cell architecture; and
transforming the first cell layout of the first cell architecture at the one or more cut lines to match the second cell layout of the second architecture.

2. The method of claim 1 , wherein the one or more cut lines run horizontally through the cell so as to enable stretching or shrinking of the cell in a height dimension.

3. The method of claim 1 , wherein the one or more cut lines run vertically through the cell so as to enable stretching or shrinking of the cell in a width dimension.

4. The method of claim 1 , further comprising specifying a resizing amount for each cut line of the one or more cut lines.

5. The method of claim 4 , wherein transforming the first cell layout of the first cell architecture comprises stretching or shrinking the first cell layout of the first cell architecture relative to the resizing amount corresponding to one or more cut lines.

6. The method of claim 4 , wherein the one or more cut lines comprise a first cut line and a second cut line, and wherein the resizing amount corresponding to the first cut line is different from the resizing amount corresponding to the second cut line.

7. The method of claim 1 , wherein the first cell layout of the first cell architecture is transformed to the second cell layout of the second architecture by resizing one or more dimensional constraints of the first cell layout to correspond to one or more corresponding dimensional constraints of the second cell layout relative to the one or more cut lines.

8. The method of claim 7 , wherein the one or more dimensional constraints include one or more of a height dimension and a width dimension.

9. The method of claim 7 , wherein resizing the one or more dimensional constraints of the first cell layout comprises stretching or shrinking the one or more dimensional constraints of the first cell layout to correspond to the one or more corresponding dimensional constraints of the second cell layout relative to the one or more cut lines.

10. The method of claim 1 , further comprising manufacturing an integrated circuit, or causing an integrated circuit to be manufactured, based on the second cell layout of the second architecture.

11. A method comprising:
obtaining a first cell layout and a second cell layout;
determining one or more cut lines within the first cell layout; and
altering the first cell layout at the one or more cut lines to conform to the second cell layout.

12. The method of claim 11 , wherein the first cell layout conforms to a first cell architecture having first dimensions, and wherein the second cell layout conforms to a second cell architecture having second dimensions that are different than the first dimensions.

13. The method of claim 12 , wherein altering the first cell layout to conform to the second cell layout comprises resizing the first dimensions of the first cell layout to match the second dimensions of the second cell layout.

14. The method of claim 11 , wherein altering the first cell layout to conform to the second cell layout comprises stretching or shrinking dimensions of the first cell layout to correspond to dimensions of the second cell layout.

15. The method of claim 11 , further comprising specifying a resizing amount for each cut line of the one or more cut lines, and wherein altering the first cell layout to conform to the second cell layout is based on the resizing amount specified for each cut line of the one or more cut lines.

16. The method of claim 15 , wherein altering the first cell layout to conform to the second cell layout comprises stretching or shrinking the first cell layout to match the second cell layout, and wherein the resizing amount refers to a stretching amount or a shrinking amount.

17. The method of claim 16 , further comprising:
identifying a portion of the first cell layout that is shiftable to form a gap having a size that is dependent on the stretching amount or the shrinking amount; and
filling the gap by interconnecting the first cell layout at each side of the gap.

18. The method of claim 11 , further comprising manufacturing an integrated circuit, or causing an integrated circuit to be manufactured, based on the second cell layout.

19. A method comprising:
obtaining a first cell layout of a cell;
identifying one or more cut lines relative to the first cell layout of the cell;
generating an output data file for the cell based on performing a sizing operation on the first cell layout, wherein the sizing operation is a resizing operation that is performed at the one or more cut lines with each cut line having a resizing amount; and
generating a second cell layout of the cell by performing a cell generation operation based on the output data file.

20. The method of claim 19 ,
wherein the resizing operation is a stretching operation with the resizing amount as a stretching amount or a shrinking operation with the resizing amount as a shrinking amount.

21. The method of claim 19 , wherein obtaining the first cell layout of the cell comprises:
identifying valid pin access layout patterns of the first cell layout of the cell, including an input/output (I/O) pin layout pattern for a first process layer and a pin access layout pattern for a second process layer;
providing one or more routing tracks in the second process layer that extend through the cell, wherein the one or more routing tracks are used for pin access connections defined by the pin access layout pattern in the second process layer; and
detecting hit points for the cell, where each hit point identifies a segment of a routing track that overlaps one or more I/O pins defined by the I/O pin layout pattern.

22. The method of claim 21 , wherein obtaining the first cell layout of the cell comprises:
determining hit point combinations for the cell, wherein each hit point combination identifies a hit point for each I/O pin of the I/O pins;
identifying an access direction for the pin access connections to the hit points along the one or more routing tracks; and
performing a design rule checking operation for fabricating an integrated circuit that is defined by the cell, wherein the design rule checking operation is performed with respect to the hit point combinations to provide an indication of the valid pin access layout patterns.

23. The method of claim 19 , wherein obtaining the first cell layout of the cell comprises:
performing a layout check operation to determine whether the first cell layout conforms to layout guidelines in reference to a target process technology and to determine whether the layout guidelines are being violated; and
analysing the cell for pin routability and layout guidelines to remove errors that occur during place and route operations.

24. The method of claim 19 , wherein obtaining the first cell layout of the cell comprises:
providing a tile database having multiple tiles that define component sections for a memory device,
wherein the tile database includes a memory array custom tile that defines an array of storage elements having a specified memory array width,
wherein the tile database includes a standard cell based tile that defines a componen

Assignees

• Advanced Risc Mach Ltd

Inventors

• De Dood Paul
• Frederick Jr Marlin Wayne
• Wang Jerry Chaoyuan
• Cline Brian Tracy
• Xu Xiaoqing
• Chen Andy Wangkun
• Chong Yew Keong
• Shore Tom
• Thyagarajan Sriram
• Yeung Gus
• Albers Daniel J
• Granda David William

Classifications

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title