Storage device buffer in system memory space

Patent metadata

Field	Value
Publication number	US-10795605-B2
Application number	US-201815959055-A
Country	US
Kind code	B2
Filing date	Apr 20, 2018
Priority date	Apr 20, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

An information handling system may include a resistive memory buffer to supplement a system main memory unit of the information handling system. A processor of the information handling system may map the resistive memory buffer as system memory, along with the system main memory unit. The processor may use the system memory, including the resistive memory buffer and the system main memory unit in executing one or more applications. The resistive memory buffer may improve performance of the information handling system, such as during hibernation and wake-up processes and memory flush processes.

First claim

What is claimed is:

1. An information handling system, comprising:
a processor;
a system main memory unit; and
a storage device, comprising:
a buffer;
a storage unit;
a first interface module; and
a controller configured to control read/write operations of the storage device, wherein the first interface module couples the processor to the controller, and wherein the controller is configured to:
write data from the storage unit into the buffer to buffer data from the storage unit;

wherein the processor is configured to map the buffer and the system main memory unit into the system memory address space, and
wherein the processor is configured to communicate with the buffer and the storage unit through the first interface module.

2. The information handling system of claim 1 , wherein the buffer comprises a non-volatile resistive memory buffer.

3. The information handling system of claim 2 , wherein the resistive memory buffer comprises at least one of magneto-resistive random-access memory (MRAM) and nano random-access memory (NRAM).

4. The information handling system of claim 1 , wherein the system main memory unit comprises dynamic random-access memory (DRAM).

5. The information handling system of claim 1 , wherein the processor is configured to address the memory buffer and the system main memory unit as a linear memory space such that a total amount of the system memory accessible to the processor is larger than the system main memory unit alone.

6. The information handling system of claim 1 , wherein the processor is configured to map the memory buffer to a segment of the system main memory unit, such that information stored in the memory buffer is redundant to information stored in the segment of the system main memory unit.

7. The information handling system of claim 6 , wherein the processor is configured to perform steps comprising:
detecting a flush condition for the segment of the system main memory unit;
copying the information stored in the memory buffer to the storage unit; and
erasing the segment of the system main memory unit without copying the information stored in the segment to the storage unit.

8. The information handling system of claim 1 , wherein the processor is configured to communicate with the memory buffer through the first interface module and independent of the controller.

9. The information handling system of claim 2 , wherein the processor is configured to perform steps comprising:
receiving, by the processor, an instruction to enter a hibernate state;
maintaining information stored in the memory buffer through the hibernate state;
detecting, by the processor, a wake condition; and
upon detection of the wake condition, using the information stored in the memory buffer to perform a rapid wake of the information handling system from the hibernate state.

10. A method, comprising:
mapping, by a processor, a system main memory unit into a system memory address space;
mapping, by the processor, a memory buffer of a storage device into the system memory address space;
utilizing, by the processor, both the system main memory unit and the memory buffer in the execution of one or more applications executed by the processor through the system memory address space,
wherein the storage device further comprises a storage unit, and
wherein utilizing the system main memory unit and the memory buffer comprises communicating, by the processor, with the memory buffer and the storage unit via an interface module of the storage device; and
controlling, by a controller coupled between the processor and a combination of the storage unit and the memory buffer, read/write operations of the storage device, the read/write operations comprising at least:
writing data from the storage unit into the memory buffer to buffer data from the storage unit.

11. The method of claim 10 , wherein mapping the memory buffer into a system memory address space comprises mapping the memory buffer to a segment of the system main memory unit so that information stored in the memory buffer is the same as information stored in the segment of the system main memory unit.

12. The method of claim 11 , further comprising:
detecting, by the processor, a flush condition for the segment of the system main memory unit;
copying the information stored in the memory buffer to the storage unit of the storage device; and
erasing the segment of the system main memory unit without copying the information stored in the segment to the storage unit of the storage device.

13. The method of claim 11 , further comprising:
receiving, by the processor, an instruction to enter a hibernate state;
maintaining information stored in the memory buffer through the hibernate state;
detecting, by the processor, a wake condition; and
upon detection of the wake condition, using the information stored in the memory buffer to perform a rapid wake of the information handling system from the hibernate state.

14. An information handling system, comprising:
a host system, comprising:
a processor and
a system main memory unit; and

a storage device, comprising:
a plurality of storage units,
a memory buffer,
a first interface module, and
a controller configured to control read/write operations of the storage device, wherein the first interface module couples the processor to the controller, and wherein the controller is configured to:
write data from the storage unit into the buffer to buffer data from the storage unit;

wherein the processor is configured to map the memory buffer into a system memory address space of the host system, and
wherein the processor is configured to communicate with the memory buffer and the plurality of storage units through the first interface module.

15. The information handling system of claim 14 , wherein the memory buffer comprises a resistive memory buffer comprising at least one of magneto-resistive random-access memory (MRAM) and nano random-access memory (NRAM).

16. The information handling system of claim 14 , wherein the storage device further includes a storage switching array coupled between the memory buffer and the plurality of storage units, wherein the storage switching array is configured to selectively couple the memory buffer to one or more of the plurality of storage units.

17. The information handing system of claim 14 , wherein the plurality of storage units comprises a plurality of solid state drives.

18. The information handling system of claim 14 , wherein the processor is configured to address the memory buffer and the system main memory unit as a linear memory space such that a total amount of the system memory accessible to the processor is larger than the system memory alone.

19. The information handling system of claim 14 , wherein the processor is further configured to map the memory buffer to a segment of the system main memory unit, so that information stored in the memory buffer is the same as information stored in the segment of the system main memory unit.

Assignees

• Dell Products Lp

Inventors

• Markow Mitchell A
• Zaretsky Lee

Classifications

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/0284

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title