Enhanced system sleep state support in servers using non-volatile random access memory

Patent metadata

Field	Value
Publication number	US-9829951-B2
Application number	US-201113976901-A
Country	US
Kind code	B2
Filing date	Dec 13, 2011
Priority date	Dec 13, 2011
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.

First claim

What is claimed is:

1. A method comprising:
intercepting, by power management firmware in a computer system, a request initiated by an operating system of the computer system for entry into a sleep state, the operating system entering a sleep-state in response thereto, the computer system comprising a processor coupled to a dynamic random access memory (DRAM) and a non-volatile system memory, the non-volatile system memory being byte addressable by the processor, the non-volatile system memory not acting as block addressable mass storage, the non-volatile system memory being accessible at cache line granularity by the processor, the operating system operating out of the non-volatile system memory, wherein the DRAM provides a portion of system memory address space for the computer system;
copying data from the DRAM to the non-volatile system memory, mapping the portion of the system memory address space from the DRAM to the non-volatile system memory, and turning off a power supply to the DRAM when the computer system transitions into the sleep state; and
upon occurrence of a wake event, waking the operating system for the computer system to resume working state operations that operate out of the non-volatile system memory without the operating system knowing that the portion of the system memory address space has been mapped to the non-volatile system memory.

2. The method of claim 1 , further comprising:
intercepting, by the power management firmware, the wake event upon its occurrence;
scheduling, by the power management firmware, a copy-back operation prior to returning control to the operating system; and
performing the copy-back operation to copy the data from the non-volatile system memory back to the DRAM in a background process after the control is returned to the operating system.

3. The method of claim 2 , further comprising:
upon completion of the copy-back operation, receiving by the power management firmware a firmware event; and
remapping the portion of the system memory address from the non-volatile system memory back to the DRAM.

4. The method of claim 1 , further comprising:
intercepting, by the power management firmware, the wake event upon the occurrence of a wake event; and
copying the data from the non-volatile system memory back to the DRAM prior to returning control to the operating system.

5. The method of claim 1 , further comprising:
prior to the entry to the sleep state, issuing by the power management firmware a command to a sleep enable register to send the request for entry to the sleep state to hardware of the computer system that performs operations of sleep state transition.

6. The method of claim 1 , wherein the non-volatile system memory provides another portion of the system memory address space.

7. The method of claim 1 , wherein the non-volatile system memory comprises the power management firmware.

8. An apparatus comprising:
a processor, the processor coupled to an interface to couple to a non-volatile system memory, the non-volatile system memory being byte addressable by the interface, the non-volatile system memory not acting as block addressable mass storage, the non-volatile system memory being accessible at cache line granularity by the interface, the processor to execute an operating system, the operating system to operate out of the non-volatile system memory; and
a power management module coupled to the processor, the non-volatile system memory and a dynamic random access memory (DRAM), wherein the DRAM is to provide a portion of system memory address space for a computer system, the power management module to intercept a request initiated by the operating system of the computer system for entry into a sleep state, copy data from the DRAM to the non-volatile system memory, map the portion of the system memory address space from the DRAM to the non-volatile system memory, and turn off the DRAM when the computer system transitions into the sleep state, and upon occurrence of a wake event and the wake up of the operating system the computer system resumes working state operations that operate out of the non-volatile system memory without the operating system knowing that the portion of the system memory address space has been mapped to the non-volatile system memory.

9. The apparatus of claim 8 , wherein the power management module is to:
intercept the wake event upon the occurrence of a wake event;
schedule a copy-back operation prior to returning control to the operating system; and
perform the copy-back operation to copy the data from the non-volatile system memory back to the DRAM in a background process after the control is returned to the operating system.

10. The apparatus of claim 9 , wherein the power management module is to:
upon completion of the copy-back operation, receive an event and
remap the portion of the system memory address from the non-volatile system memory back to the DRAM.

11. The apparatus of claim 8 , wherein the power management module is to:
intercept the wake event upon the occurrence of a wake event; and
copy the data from the non-volatile system memory back to the DRAM prior to returning control to the operating system.

12. The apparatus of claim 8 , wherein:
the power management module is to, prior to the entry to the sleep state, issue a command to a sleep enable register to send the request for entry to the sleep state to hardware of the computer system that performs operations of sleep state transition.

13. The apparatus of claim 8 , wherein the non-volatile system memory is to provide another portion of the system memory address space.

14. The apparatus of claim 8 , wherein the power management module comprises power management firmware located in the non-volatile system memory.

15. The apparatus of claim 8 , wherein the power management module comprises one or more of the following: software, firmware, and hardware.

16. The apparatus of claim 8 , further comprising a mechanism to trap a software request to enter the sleep state and defer the software request until the DRAM to the non-volatile system memory copy is completed, wherein the mechanism comprises firmware, hardware or a combination of the two.

17. A system comprising:
a processor in a computer system;
a non-volatile system memory coupled to the processor, the non-volatile system memory being byte addressable by the processor, the non-volatile system memory not acting as block addressable mass storage, the non-volatile system memory being accessible by the processor at cache line granularity, an operating system of the computer system to operate out of the non-volatile system memory;
a dynamic random access memory (DRAM) that provides a portion of system memory address space for the computer system; and
a power management module coupled to the processor, the non-volatile system memory and the DRAM, the power management module to intercept a request initiated by the operating system of the computer system for entry into a sleep state, copy data from the DRAM to the non-volatile system memory, map the portion of the system address space from the DRAM to the non-volatile system memory, and turn off the DRAM when the computer system transitions into the sleep state, and upon occurrence of a wake event and the wake up of the operating system, the computer system resumes working state operations that operate out of the non-volatile system memory without the operating system knowing that the portion of the system address space has been mapped to the non-volatile system memory.

18. The system o

Assignees

• Kumar Mohan J
• Nachimuthu Murugasamy K
• Intel Corp

Inventors

• Kumar Mohan J
• Nachimuthu Murugasamy K

Classifications

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title