Write bandwidth enhancement scheme in phase change memory
US-2018061492-A1 · Mar 1, 2018 · US
Memory device
US10790443B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10790443-B2 |
| Application number | US-201815909125-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 1, 2018 |
| Priority date | Sep 15, 2017 |
| Publication date | Sep 29, 2020 |
| Grant date | Sep 29, 2020 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A memory device includes a first conductive layer and a second conductive layer. A variable resistance layer is disposed between the first conductive layer and the second conductive layer and includes a first layer containing a semiconductor or a first metal oxide, and a second layer containing a second metal oxide. A phase-change layer is disposed either between the first conductive layer and the variable resistance layer or between the second conductive layer and the variable resistance layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory device comprising: a first conductive layer; a second conductive layer; a variable resistance layer disposed between the first conductive layer and the second conductive layer, and including a first layer comprising a semiconductor or a first metal oxide, and a second layer comprising a second metal oxide; and a phase-change layer disposed between the first conductive layer and the second conductive layer, the phase-change layer being connected to (i) the first conductive layer and (ii) either the first layer of the variable resistance layer or the second layer of the variable resistance layer. 2. The memory device according to claim 1 , wherein the phase-change layer is a phase-change layer disposed between the first conductive layer and the variable resistance layer, and the memory device further comprising a second phase-change layer disposed between the second conductive layer and the variable resistance layer. 3. The memory device according to claim 1 , wherein the second layer has a resitivity lower than a resitivity of the first layer, and wherein the first layer is arranged between the first conductive layer and the second layer. 4. The memory device according to claim 1 , wherein the first layer comprises an amorphous metal oxide and the second layer comprises a crystalline metal oxide. 5. The memory device according to claim 1 , wherein the phase-change layer comprises a material having a property of entering an amorphous state by being heated to 700° C. or lower. 6. The memory device according to claim 1 , wherein the phase-change layer comprises a compound of germanium (Ge), tellurium (Te), and antimony (Sb).
Assignees
Inventors
Classifications
Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title
- G11C13/0007Primary
comprising metal oxide memory material, e.g. perovskites · CPC title
Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title
Array using an access device for each cell which being not a transistor and not a diode · CPC title
Array wherein the access device being a transistor · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US10790443B2 cover?
- A memory device includes a first conductive layer and a second conductive layer. A variable resistance layer is disposed between the first conductive layer and the second conductive layer and includes a first layer containing a semiconductor or a first metal oxide, and a second layer containing a second metal oxide. A phase-change layer is disposed either between the first conductive layer and …
- Who is the assignee on this patent?
- Toshiba Memory Corp
- What technology area does this patent fall under?
- Primary CPC classification G11C13/0007. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 29 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).