Method for forming horizontal nanowires and devices manufactured thereof

Patent metadata

Field	Value
Publication number	US-10790382-B2
Application number	US-201715845300-A
Country	US
Kind code	B2
Filing date	Dec 18, 2017
Priority date	Dec 23, 2016
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer. The horizontal nanowires become suspended starting from the top and the cladding layer is removed, after the bottom horizontal nanowire becomes suspended.

First claim

What is claimed is:

1. A method for forming horizontal nanowires, the method comprising:
providing a substrate comprising a dielectric layer and a fin structure, wherein the fin structure comprises a portion protruding from the dielectric layer, and wherein the protruding portion is partially un-masked and comprises a multi-layer stack that comprises a layer of a first material stacked alternately and repeatedly with a layer of a second material, wherein layers of a portion of the multilayer stack of the partially un-masked protruding portion have a non-uniform size; and
forming horizontal nanowires, wherein the forming comprises performing a cycle comprising:
selectively removing the first material such that a horizontal nanowire of the second material is suspended over a remaining portion of the partially un-masked protruding portion;
forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered;
providing, selectively, a metal cladding layer on the suspended horizontal nanowire; and
removing the sacrificial layer.

2. The method of claim 1 , wherein the horizontal nanowires formed in the cycle become suspended starting from a top horizontal nanowire to a bottom horizontal nanowire.

3. The method of claim 2 , further comprising:
removing the cladding layer after the bottom horizontal nanowire becomes suspended.

4. The method of claim 1 , wherein the substrate is rotated during the forming of the sacrificial layer.

5. The method of claim 1 , wherein the sacrificial layer is a spin-on material and is self-planarizing.

6. The method of claim 1 , wherein the sacrificial layer is formed as a spin-on-carbon layer.

7. The method of claim 1 , wherein the selective removal of the first material is cyclic and comprises:
oxidizing the first material and the second material; and
performing an etching process, wherein parameters of the etching process are chosen to remove an oxide of the first material is faster than an oxide of the second material.

8. The method of claim 7 , wherein the etching process is a dry plasma etching process.

9. The method of claim 1 , wherein providing, selectively, the cladding layer comprises performing an electro-less deposition or an atomic layer deposition.

10. The method of claim 1 , wherein the first material comprises Si and Ge, and the second material comprises Si.

11. The method of claim 1 , wherein the first material comprises Si and the second material comprises Si and Ge.

12. The method of claim 1 , further comprising:
providing a gate stack, surrounding the suspended horizontal nanowires, wherein the gate stack comprises a gate insulator and a gate metal provided on the gate insulator.

13. A semiconductor structure comprising:
a substrate comprising a dielectric layer; and
a fin structure comprising a portion protruding from the dielectric layer, wherein the protruding portion is partially un-masked, and wherein the partially un-masked protruding portion comprises:
a multilayer stack that includes a layer of a first material stacked alternately and repeatedly with a layer of a second material, and a horizontal nanowire of the second material that is covered with a metal cladding layer, wherein the horizontal nanowire is suspended over the multilayer stack and a sacrificial layer covering the multilayer stack, and wherein layers of a portion of the multilayer stack of the partially un-masked protruding portion have a non-uniform size.

14. The structure of claim 13 , wherein the sacrificial layer is formed as a spin-on-carbon layer.

15. The structure of claim 13 , wherein:
a diameter of the horizontal nanowires is substantially the same.

16. The structure of claim 13 , wherein the first material comprises Si and Ge, and the second material comprises Si.

17. The structure of claim 13 , wherein the first material comprises Si and the second material comprises Si and Ge.

18. The structure of claim 13 , further comprising:
a gate stack, surrounding the suspended horizontal nanowires, wherein the gate stack comprises a gate insulator and a gate metal provided on the gate insulator.

19. A semiconductor structure comprising:
a substrate comprising a dielectric layer; and
a fin structure comprising a portion protruding from the dielectric layer, wherein the protruding portion comprises a multilayer stack that includes a layer of a first material stacked alternately and repeatedly with a layer of a second material, wherein the protruding portion is partially un-masked, and wherein the partially un-masked protruding portion comprises:
at least one horizontal nanowire of the second material suspended over a remaining portion of the multilayer stack that includes layers of the first material and second material, wherein the at least one horizontal nanowire is covered with a metal cladding layer, wherein a sacrificial layer covers the remaining portion of the multilayer stack and leaves the at least one horizontal nanowire uncovered, and wherein layers of a portion of the multilayer stack of the partially un-masked protruding portion have a non-uniform size.

20. The structure of claim 19 , wherein the fin structure includes non-protruding portion embedded in the dielectric layer.

21. The structure of claim 19 , wherein the protruding portion includes a partially masked portion, and wherein a top and sidewalls of the partially masked portion of the protruding portion are masked.

Assignees

• Imec Vzw

Inventors

• Chan Boon Teik
• Armini Silvia
• Camerotto Elisabeth
• Tao Zheng

Classifications

• H10D62/364

  of IGFETs · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title