Intelligent semiconductor device having SiGe quantum well

Patent metadata

Field	Value
Publication number	US-10790359-B2
Application number	US-201916451639-A
Country	US
Kind code	B2
Filing date	Jun 25, 2019
Priority date	Sep 12, 2018
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

An intelligent semiconductor device has a body region in which a channel is formed. The body region has a heterojunction of different semiconductor layers and a quantum well formed in a semiconductor layer in contact with a drain. The quantum well is configured to store holes generated in a depletion layer of the drain region and imitate a short-term memory, and to convert the short-term memory into a long-term memory by enabling holes to be injected into a charge storage layer when the holes stored in quantum well exceed a specific threshold value. It is possible to fabricate with a bulk semiconductor substrate and utilize the conventional CMOS technology.

First claim

What is claimed is:

1. An intelligent semiconductor device comprising:
a body region having a first semiconductor layer, a second semiconductor layer, and a heterojunction between the first and the second semiconductor layers;
a biasing gate and a control gate spaced apart on the body region and crossing the heterojunction;
a first gate insulating layer provided between the biasing gate and the body region;
a second gate insulating layer having a charge storage layer formed between the control gate and the body region;
a source region provided at one end of the first semiconductor layer; and
a drain region provided at one end of the second semiconductor layer.

2. The intelligent semiconductor device of claim 1 , wherein the second semiconductor layer has a smaller energy band gap than the first semiconductor layer.

3. The intelligent semiconductor device of claim 2 , wherein the first semiconductor layer is formed to protrude vertically on the source region, and wherein the second semiconductor layer and the drain region are sequentially stacked on the first semiconductor layer.

4. The intelligent semiconductor device of claim 2 , wherein the body region is formed by vertically stacking the first semiconductor layer and the second semiconductor layer in a polygonal columnar shape on the source region, and wherein the biasing gate and the control gate are spaced apart from each other on sides of the polygonal columnar shape and formed of one or more, respectively.

5. The intelligent semiconductor device of claim 2 , wherein the source region and the drain region are horizontally spaced apart on a semiconductor substrate, and wherein the first semiconductor layer and the second semiconductor layer are formed horizontally between the source region and the drain region.

6. The intelligent semiconductor device of claim 2 , wherein the source region and the drain region are horizontally spaced apart on a semiconductor substrate, wherein the first semiconductor layer and the second semiconductor layer of the body region have a polygonal horizontal bar shape between the source region and the drain region, and wherein the biasing gate and the control gate are spaced apart from each other on sides of the polygonal horizontal bar shape, the biasing gate and the control gate being one or more, respectively.

7. The intelligent semiconductor device of claim 1 , wherein the second semiconductor layer has a quantum well between a depletion layer of the drain region and the heterojunction, and wherein the quantum well is configured to store holes generated in the depletion layer and imitate a short-term memory, the quantum well converting the short-term memory into a long-term memory by enabling holes to be injected into the charge storage layer when the holes stored in the quantum well exceed a specific threshold value.

8. The intelligent semiconductor device of claim 5 , wherein the first semiconductor layer is a silicon layer, and wherein the second semiconductor layer is a silicon germanium layer.

9. The intelligent semiconductor device of claim 8 , wherein the silicon layer is formed of a bulk silicon substrate, the source region being formed in the bulk silicon substrate.

10. The intelligent semiconductor device of claim 8 , wherein the biasing gate and the control gate cover the depletion layer and are formed to a distance away from the source region.

11. The intelligent semiconductor device of claim 2 , wherein the second semiconductor layer has a quantum well between a depletion layer of the drain region and the heterojunction, and wherein the quantum well is configured to store holes generated in the depletion layer and imitate a short-term memory, the quantum well converting the short-term memory into a long-term memory by enabling holes to be injected into the charge storage layer when the holes stored in quantum well exceed a specific threshold value.

12. The intelligent semiconductor device of claim 3 , wherein the second semiconductor layer has a quantum well between a depletion layer of the drain region and the heterojunction, and wherein the quantum well is configured to store holes generated in the depletion layer and imitate a short-term memory, the quantum well converting the short-term memory into a long-term memory by enabling holes to be injected into the charge storage layer when the holes stored in quantum well exceed a specific threshold value.

13. The intelligent semiconductor device of claim 4 , wherein the second semiconductor layer has a quantum well between a depletion layer of the drain region and the heterojunction, and wherein the quantum well is configured to store holes generated in the depletion layer and imitate a short-term memory, the quantum well converting the short-term memory into a long-term memory by enabling holes to be injected into the charge storage layer when the holes stored in quantum well exceed a specific threshold value.

14. The intelligent semiconductor device of claim 5 , wherein the second semiconductor layer has a quantum well between a depletion layer of the drain region and the heterojunction, and wherein the quantum well is configured to store holes generated in the depletion layer and imitate a short-term memory, the quantum well converting the short-term memory into a long-term memory by enabling holes to be injected into the charge storage layer when the holes stored in quantum well exceed a specific threshold value.

15. The intelligent semiconductor device of claim 6 , wherein the second semiconductor layer has a quantum well between a depletion layer of the drain region and the heterojunction, and wherein the quantum well is configured to store holes generated in the depletion layer and imitate a short-term memory, the quantum well converting the short-term memory into a long-term memory by enabling holes to be injected into the charge storage layer when the holes stored in quantum well exceed a specific threshold value.

Assignees

• Univ Gachon Ind Acad Coop Found
• Gachon Univ Of Industry Academic Cooperation

Inventors

• Cho Seongjae
• Yu Eunseon

Classifications

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title