Reducing gate induced drain leakage in DRAM wordline

Patent metadata

Field	Value
Publication number	US-10790287-B2
Application number	US-201816204300-A
Country	US
Kind code	B2
Filing date	Nov 29, 2018
Priority date	Nov 29, 2018
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.

First claim

What is claimed is:

1. A memory device comprising:
a substrate with a substrate surface having a plurality of trenches extending a depth into the substrate, each trench including a bottom and sidewall;
a gate oxide layer on the bottom and sidewall of the trenches;
a recessed metal layer on the gate oxide layer, the recessed metal layer comprising a first work-function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trench; and
a second work-function metal layer on the recessed metal layer, the second work-function metal layer substantially free of polysilicon and/or doped polysilicon and the second work-function metal layer comprising a material having a work-function less than 4.3 eV.

2. The memory device of claim 1 , wherein the first work-function metal layer is formed on the gate oxide layer on the sidewall and bottom of the plurality of trenches and the bulk metal layer is formed on the first work-function metal layer.

3. The memory device of claim 1 , wherein the first work-function metal layer comprises a metal nitride.

4. The memory device of claim 1 , wherein the first work-function metal layer comprises one or more of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN/TiN, or WN/TiN.

5. The memory device of claim 1 , wherein the bulk metal layer comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).

6. The memory device of claim 1 , wherein the first work-function metal layer comprises a material having a work-function greater than or equal to 4.3 eV.

7. The memory device of claim 1 , wherein the second work-function metal layer comprises a metal carbide or metal silicide with one or more metal selected from aluminum (Al), gallium (Ga), indium (In) or thallium (Tl).

8. The memory device of claim 1 , wherein the second work-function metal layer has a top surface within the depth of the plurality of trenches.

9. The memory device of claim 8 , further comprising an insulating layer in the plurality of trenches on the second work-function metal layer, the insulating layer having a top surface substantially coplanar with the substrate surface.

10. A memory cell comprising:
a recessed access device; and
a word line electrically coupled to the recessed access device, the word line comprising a substrate with a substrate surface having a plurality of trenches extending a depth into the substrate, each trench including a bottom and sidewall; a gate oxide layer on the bottom and sidewall of the trenches; a recessed metal layer on the gate oxide layer, the recessed metal layer comprising a first work-function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trench; and a second work-function metal layer on the recessed metal layer, the second work-function metal layer substantially free of polysilicon and/or doped polysilicon and the second work-function metal layer comprising a material having a work-function less than 4.3 eV.

Assignees

• Applied Materials Inc

Inventors

• Kang Sung-Kwan
• Lee Gill Yong
• Yu Sang Ho
• Chen Shih Chung
• Anthis Jeffrey W

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title