Stacked channel structures for MOSFETs

Patent metadata

Field	Value
Publication number	US-10790281-B2
Application number	US-201515773325-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Dec 3, 2015
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.

First claim

The invention claimed is:

1. A stacked channel structure, comprising:
a semiconductor substrate having a substrate lattice constant;
a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region;
a first channel material of a first transistor, wherein the first channel material is in the lower region, the first channel material has a first lattice constant, and the first lattice constant is different from the substrate lattice constant;
a second channel material of a second transistor, wherein the second channel material is in the upper region, the second channel material has a second lattice constant, the second lattice constant is different from the substrate lattice constant;
source/drain (S/D) regions, wherein the S/D regions include a dopant in the second channel material;
a first intermediate material between the first channel material and the semiconductor substrate; and
a second intermediate material between the first channel material and the second channel material;
wherein the first intermediate material or the second intermediate material includes yttria stabilized zirconia (YSZ).

2. The stacked channel structure of claim 1 , wherein the first lattice constant is greater than the substrate lattice constant.

3. The stacked channel structure of claim 2 , wherein the second lattice constant is greater than the substrate lattice constant.

4. The stacked channel structure of claim 2 , wherein the second lattice constant is less than the substrate lattice constant.

5. The stacked channel structure of claim 1 , wherein the first lattice constant is less than the substrate lattice constant.

6. The stacked channel structure of claim 5 , wherein the second lattice constant is greater than the substrate lattice constant.

7. The stacked channel structure of claim 5 , wherein the second lattice constant is less than the substrate lattice constant.

8. The stacked channel structure of claim 1 , wherein the first intermediate material has a thickness between the first channel material and the semiconductor substrate, and the thickness is less than 20 nm.

9. The stacked channel structure of claim 1 , wherein the second intermediate material has a thickness between the first channel material and the second channel material, and the thickness is less than 20 nm.

10. The stacked channel structure of claim 1 , wherein the semiconductor substrate includes relaxed silicon germanium (SiGe).

11. The stacked channel structure of claim 1 , wherein at least one of the first and second transistors is an n-type metal oxide semiconductor (NMOS) device, the channel material associated with that at least one transistor is under tension, and the tension has a magnitude greater than or equal to 250 MPa.

12. The stacked channel structure of claim 1 , wherein at least one of the first and second transistors is a p-type metal oxide semiconductor (PMOS) device, the channel material associated with the PMOS device is under compression, and the compression has a magnitude greater than or equal to 250 MPa.

13. The stacked channel structure of claim 1 , wherein the dopant in the S/D regions is an implanted dopant or an in-diffused dopant.

14. An electronic component, comprising:
a circuit element that includes:
a semiconductor substrate;
a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region;
a first strained channel material of a first transistor, wherein the first strained channel material is in the lower region;
a first intermediate material between the first strained channel material and the semiconductor substrate;
a second strained channel material of a second transistor, wherein the second strained channel material is in the upper region, and the first strained channel material is between the second strained channel material and the semiconductor substrate;
a second intermediate material between the first strained channel material and the second strained channel material;
source/drain (S/D) regions, wherein the S/D regions include a dopant in the second strained channel material; and
a conductive pathway between the first and second transistors;
wherein (1) at least one of the first and second transistors is an n-type metal oxide semiconductor (NMOS) device, the strained channel material associated with that at least one transistor is under tension, and the tension has a magnitude greater than or equal to 250 MPa, or (2) at least one of the first and second transistors is a p-type metal oxide semiconductor (PMOS) device, the strained channel material associated with that at least one transistor is under compression, and the compression has a magnitude greater than or equal to 250 MPa.

15. The electronic component of claim 14 , wherein the circuit element is included in a processing device of the electronic component, and the electronic component further includes a memory device coupled to the processing device.

16. The electronic component of claim 15 , wherein:
the first intermediate material or the second intermediate material includes a crystalline insulator.

17. The electronic component of claim 16 , wherein the first intermediate material or the second intermediate material includes yttria stabilized zirconia (YSZ).

18. The electronic component of claim 15 , further comprising:
an antenna;
a communication chip;
a display; and
a battery.

19. The electronic component of claim 15 , further comprising a graphics processing unit, a power amplifier, a global positioning system receiver, or a voltage regulator.

20. The electronic component of claim 15 , wherein the dopant in the S/D regions is an implanted dopant or an in-diffused dopant.

21. The electronic component of claim 14 , wherein:
the first intermediate material or the second intermediate material includes a crystalline insulator.

22. The electronic component of claim 21 , wherein the first intermediate material or the second intermediate material includes yttria stabilized zirconia (YSZ).

23. The electronic component of claim 14 , wherein the dopant in the S/D regions is an implanted dopant or an in-diffused dopant.

24. A method of manufacturing a stacked channel structure, comprising:
providing a semiconductor substrate having a substrate lattice constant;
providing a first intermediate layer on the semiconductor substrate;
providing a first channel material on the first intermediate layer, the first channel material having a first lattice constant different from the substrate lattice constant;
providing a second intermediate layer on the first channel material;
providing a second channel material on the second intermediate layer, the second channel material having a second lattice constant different from the substrate lattice constant;
forming a fin extending away from the semiconductor substrate, wherein the first channel material is in a lower region of the fin and the second channel material is in an upper region of the fin;
etching the second channel material; and
after etching the second channel material, forming source/drain (S/D) regions by implanting or in-diffusing a dopant into the second channel material.

25. The method of claim 24 , wherein the second intermediate layer is a marker layer.

Assignees

• Intel Corp

Inventors

• Mehandru Rishabh
• Kotlyar Roza
• Cea Stephen M
• Keys Patrick H

Classifications

• H10D88/01

  Manufacture or treatment · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title