Fin field effect transistor fabrication and devices having inverted T-shaped gate

Patent metadata

Field	Value
Publication number	US-10784365-B2
Application number	US-201916264955-A
Country	US
Kind code	B2
Filing date	Feb 1, 2019
Priority date	Jun 3, 2016
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

First claim

What is claimed is:

1. A fin field effect transistor (finFET) having an inverted-T gate, comprising;
a first gate spacer layer and a first source/drain spacer layer on one or more fins, wherein the first gate spacer layer is adjacent to the first source/drain spacer layer;
a second gate spacer layer and a second source/drain spacer layer on the one of the one or more fins, wherein the second gate spacer layer is adjacent to the second source/drain spacer layer, and the first gate spacer layer is opposite the second gate spacer layer, wherein the first gate spacer layer includes a first recessed cavity, and the second gate spacer layer includes a second recessed cavity.

2. The finFET of claim 1 , wherein the first recessed cavity extends to an inward facing sidewall of the first source/drain spacer layer, and the second recessed cavity extends to an inward facing sidewall of the second source/drain spacer layer.

3. The finFET of claim 2 , wherein the first gate spacer layer has a thickness in a range of about 1.5 nm to about 3 nm, and the second gate spacer layer has a thickness in a range of about 1.5 nm to about 3 nm.

4. The finFET of claim 2 , wherein the first recessed cavity has a height in a range of about 5 nm to about 15 nm, and the second recessed cavity has a height in a range of about 5 nm to about 15 nm.

5. The finFET of claim 4 , wherein a thinner portion of the first source/drain spacer layer has a thickness in the range of about 2 nm to about 4 nm, and a thinner portion of the second source/drain spacer layer has a thickness in the range of about 2 nm to about 4 nm.

6. The finFET of claim 2 , wherein the first gate spacer layer and the second gate spacer layer are each made of a material selected from the group consisting of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), and combinations thereof.

7. The finFET of claim 6 , wherein the first source/drain spacer layer and the second source/drain spacer layer are each made of a material selected from the group consisting of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), and combinations thereof, wherein the material of the first source/drain spacer layer and the second source/drain spacer layer are different from the material selected for the first gate spacer layer and the second gate spacer layer.

8. The finFET of claim 7 , further comprising a gate dielectric layer that occupies the first recessed cavity and the second recessed cavity to form an inverted-T gate structure.

9. The finFET of claim 8 , further comprising a first source/drain formed on a first end of at least one of the one or more fins, and a second source/drain formed on a second end of the at least one of the one or more fins, wherein the first source/drain is adjacent to the first source/drain spacer layer, and the second source/drain is adjacent to the second source/drain spacer layer.

10. A fin field effect transistor (finFET) having an inverted-T gate, comprising;
a first gate spacer layer and a first source/drain spacer layer on one or more fins, wherein the first gate spacer layer is adjacent to the first source/drain spacer layer;
a second gate spacer layer and a second source/drain spacer layer on the one of the one or more fins, wherein the second gate spacer layer is adjacent to the second source/drain spacer layer, and the first gate spacer layer is opposite the second gate spacer layer, wherein the first gate spacer layer includes a first recessed cavity that extends to an inward facing sidewall of the first source/drain spacer layer, and the second gate spacer layer includes a second recessed cavity that extends to an inward facing sidewall of the second source/drain spacer layer, wherein the first gate spacer layer is separated from the second gate spacer layer by a width of about 10 nm to about 50 nm.

11. The finFET of claim 10 , wherein the first recessed cavity extends to an inward facing sidewall of the first source/drain spacer layer, and the second recessed cavity extends to an inward facing sidewall of the second source/drain spacer layer.

12. The finFET of claim 11 , further comprising a gate dielectric layer that occupies the first recessed cavity and the second recessed cavity to form an inverted-T gate structure.

13. The finFET of claim 12 , wherein the first gate spacer layer and the second gate spacer layer are each made of a material selected from the group consisting of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), and combinations thereof.

14. The finFET of claim 12 , wherein the first gate spacer layer has a thickness in a range of about 1.5 nm to about 3 nm, and the second gate spacer layer has a thickness in a range of about 1.5 nm to about 3 nm.

15. The finFET of claim 14 , wherein gate dielectric layer is a high-K dielectric material.

16. A fin field effect transistor (finFET) having an inverted-T gate, comprising;
a first gate spacer layer and a first source/drain spacer layer on one or more fins, wherein the first gate spacer layer is adjacent to the first source/drain spacer layer;
a second gate spacer layer and a second source/drain spacer layer on the one of the one or more fins, wherein the second gate spacer layer is adjacent to the second source/drain spacer layer, and the first gate spacer layer is opposite the second gate spacer layer, wherein the first gate spacer layer includes a first recessed cavity that extends to an inward facing sidewall of the first source/drain spacer layer, and the second gate spacer layer includes a second recessed cavity that extends to an inward facing sidewall of the second source/drain spacer layer, wherein the first gate spacer layer has a thickness in a range of about 1.5 nm to about 3 nm, and the second gate spacer layer has a thickness in a range of about 1.5 nm to about 3 nm;
a gate dielectric layer that occupies the first recessed cavity and the second recessed cavity; and
a gate metal fill on the gate dielectric layer to form an inverted-T gate structure.

17. The finFET of claim 16 , wherein the first recessed cavity extends to an inward facing sidewall of the first source/drain spacer layer, and the second recessed cavity extends to an inward facing sidewall of the second source/drain spacer layer.

18. The finFET of claim 17 , further comprising a first source/drain formed on a first end of at least one of the one or more fins, and a second source/drain formed on a second end of the at least one of the one or more fins, wherein the first source/drain is adjacent to the first source/drain spacer layer, and the second source/drain is adjacent to the second source/drain spacer layer.

19. The finFET of claim 18 , wherein the first source/drain spacer layer and the second source/drain spacer layer each include a thinner portion and a step.

20. The finFET of claim 19 , wherein the thinner portion of the first source/drain spacer layer has a thickness in the range of about 2 nm to about 4 nm, and wherein the step in the first source/drain spacer layer and the second source/drain spacer layer each are at the same height as a top surface of the adjacent source/drain on the one or more fins.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Liu Zuoguang
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/268

  of silicon-containing layers · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title