Multi-chip package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9257309-B2
Application number	US-201414250360-A
Country	US
Kind code	B2
Filing date	Apr 10, 2014
Priority date	Dec 9, 2011
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.

First claim

What is claimed is:

1. A method of manufacturing a multi-chip package, the method comprising:
forming a supporting member on a side surface of a first semiconductor chip;
stacking the first semiconductor chip with the supporting member formed on the side thereof on a package substrate;
forming an auxiliary bonding pad which extends from a first bonding pad of the first semiconductor chip along an upper surface of the supporting member; and
stacking a second semiconductor chip, wherein the second semiconductor chip extends beyond the side surface of the first semiconductor chip and is disposed on the first semiconductor chip and the supporting member.

2. The method of claim 1 , wherein forming the supporting member comprises:
attaching the first semiconductor chip to an upper surface a supporting plate;
forming a preliminary supporting member on the upper surface of supporting plate to cover an upper surface of the first semiconductor chip.

3. The method of claim 2 , wherein forming the supporting member further comprises:
removing a top portion of the preliminary supporting member until the upper surface of the first semiconductor chip is exposed.

4. The method of claim 1 , further comprising:
forming a molding member on an upper surface of the package substrate to cover the first semiconductor chip and the second semiconductor chip.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hee-Jin
• Lee Woo-Dong

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title