Semiconductor devices having 3-dimensional inductive structures

Patent metadata

Field	Value
Publication number	US-10784192-B2
Application number	US-201816183057-A
Country	US
Kind code	B2
Filing date	Nov 7, 2018
Priority date	Nov 7, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component.

First claim

We claim:

1. An inductive structure comprising:
a substrate;
a plurality of tiers arranged in a stack on the substrate, wherein—
the stack of tiers includes a stepped portion,
individual ones of the tiers include (a) a peripheral region that is exposed from the stack at the stepped portion, (b) a first layer, and (c) a second layer over the first layer, and
the first layer includes an electrically insulative material;

a plurality of loops of electrically conductive material, wherein the loops are formed in corresponding ones of the second layers, wherein the loops are electrically accessible at the stepped portion, and wherein the loops are electrically coupled together to form an inductor;
a metallization structure; and
a plurality of conductive members extending between the stepped portion of the stack and the metallization structure, wherein the conductive members electrically couple the metallization structure to the loops.

2. An inductive structure comprising:
a substrate;
a plurality of tiers arranged in a stack on the substrate, wherein—
the stack of tiers includes a stepped portion,
individual ones of the tiers include (a) a peripheral region that is exposed from the stack at the stepped portion, (b) a first layer, and (c) a second layer over the first layer, and
the first layer includes an electrically insulative material;

a plurality of loops of electrically conductive material, wherein the loops are formed in corresponding ones of the second layers, wherein the loops are electrically accessible at the stepped portion, and wherein the loops are electrically coupled together to form an inductor;
a metallization structure;
a plurality of conductive members extending between the stepped portion of the stack and the metallization structure, wherein the conductive members electrically couple the metallization structure to the loops; and
an oxide material over the stepped portion of the stack, wherein the conductive members extend generally vertically through the oxide material.

3. The inductive structure of claim 1 wherein individual ones of the loops include multiple planar windings.

4. The inductive structure of claim 1 wherein the loops are electrically coupled together in series.

5. The inductive structure of claim 1 wherein—
the electrically insulative material is an oxide material;
the electrically conductive material is tungsten; and
the second layers further include a nitride material at least partially around the tungsten.

6. The inductive structure of claim 1 wherein the plurality of tiers includes more than one hundred tiers.

7. The inductive structure of claim 1 wherein the loops have different radii.

8. The inductive structure of claim 1 wherein the inductor is configured to be electrically coupled to a 3D-NAND memory array.

9. The inductive structure of claim 1 , further comprising a circuit component carried by the substrate, wherein the circuit component is electrically coupled to the inductor.

10. The inductive structure of claim 9 wherein the circuit component is a bond pad.

11. The inductive structure of claim 1 wherein the inductor forms a portion of an RLC shunt.

12. The inductive structure of claim 1 wherein the inductor forms a portion of an electrostatic discharge (ESD) circuit.

13. The inductive structure of claim 12 wherein the inductor is configured to trigger the ESD circuit.

14. The inductive structure of claim 1 wherein the conductive members are conductive columns.

15. The inductive structure of claim 2 wherein individual ones of the loops include multiple planar windings.

16. The inductive structure of claim 2 wherein the loops are electrically coupled together in series.

17. The inductive structure of claim 2 wherein—
the electrically insulative material is an oxide material;
the electrically conductive material is tungsten; and
the second layers further include a nitride material at least partially around the tungsten.

18. The inductive structure of claim 2 wherein the plurality of tiers includes more than one hundred tiers.

19. The inductive structure of claim 2 wherein the loops have different radii.

20. The inductive structure of claim 2 wherein the inductor is configured to be electrically coupled to a 3D-NAND memory array.

Assignees

• Micron Technology Inc

Inventors

• Davis James E
• Duesman Kevin G

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title