Method of etching microelectronic mechanical system features in a silicon wafer

Patent metadata

Field	Value
Publication number	US-10784115-B2
Application number	US-201916507272-A
Country	US
Kind code	B2
Filing date	Jul 10, 2019
Priority date	Mar 13, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.

First claim

What is claimed is:

1. A method of etching features in a silicon wafer, the method comprising:
placing a patterned mask on a top surface and a bottom surface of the silicon wafer, the patterned mask having a lower etch rate than an etch rate of the silicon wafer;
etching one or more top surface features into the top surface of the silicon wafer through the patterned mask to a target depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface;
coating the top surface and the one or more top surface features with a metallic coating; and
etching one or more bottom surface features into the bottom surface of the silicon wafer through the patterned mask to the target depth plane.

2. The method of claim 1 , further comprising mounting the silicon wafer to a carrier substrate before etching the one or more bottom surface features.

3. The method of claim 1 , wherein the one or more top surface features are selected from one or more inlet manifolds, one or more auxiliary channels, one or more cooling fluid inlet channels, and one or more top portions of one or more cooling fluid outlet channels.

4. The method of claim 3 , wherein:
the patterned mask comprises one or more top surface features that are removed from a patterned mask top surface located on the top surface of the silicon wafer, and
the one or more top surface features correspond to the one or more inlet manifolds and the one or more top portions of the one or more cooling fluid outlet channels.

5. The method of claim 1 , wherein the one or more bottom surface features are selected from one or more inlet holes and one or more bottom portions of one or more cooling fluid outlet channels.

6. The method of claim 5 , wherein:
the patterned mask comprises one or more bottom surface features that are removed from a patterned mask bottom surface located on the bottom surface of the silicon wafer, and
the one or more bottom surface features correspond to the one or more inlet holes and the one or more bottom portions of the one or more cooling fluid outlet channels.

7. The method of claim 1 , wherein the one or more top surface features and the one or more bottom surface features are etched using anisotropic deep silicon etching.

8. The method of claim 1 , wherein the metallic coating is aluminum.

9. The method of claim 8 , wherein coating the top surface and the one or more top surface features comprises coating via an aluminum sputtering process.

10. A method of etching one or more features in a silicon wafer, the method comprising:
placing a patterned mask on a top surface and a bottom surface of the silicon wafer, the patterned mask having a lower etch rate than an etch rate of the silicon wafer;
etching one or more bottom surface features into the bottom surface of the silicon wafer through the patterned mask to a target depth plane located between the top surface and the bottom surface of the silicon wafer at a target depth from the top surface;
coating the bottom surface and the one or more bottom surface features etched into the bottom surface with a metallic coating; and
etching one or more top surface features into the top surface of the silicon wafer through the patterned mask to the target depth plane.

11. The method of claim 10 , further comprising mounting the silicon wafer to a carrier substrate before etching the one or more features into the top surface of the silicon wafer.

12. The method of claim 10 , wherein the metallic coating is an aluminum coating.

13. The method of claim 10 , wherein coating the bottom surface and the one or more bottom surface features comprises coating via an aluminum sputtering process.

14. The method of claim 10 , wherein the one or more features are etched using an anisotropic silicon etching technique.

15. A method of etching one or more through-features into a silicon wafer comprising a top surface and a bottom surface and coated with a patterned mask, wherein the one or more through-features comprise one or more nozzle through-holes, an outlet plenum, and a cooling fluid outlet, the method comprising:
etching a bottom portion of the one or more nozzle through-holes from the bottom surface to a nozzle target depth through the patterned mask;
etching the cooling fluid outlet from the bottom surface to a plenum target depth through the patterned mask;
coating the bottom surface and the bottom portion of the one or more nozzle through-holes and the cooling fluid outlet with a metallic coating;
etching a top portion of the one or more nozzle through-holes from the top surface to the nozzle target depth; and
etching the outlet plenum from the top surface to the plenum target depth, wherein:
the first of the one or more through-features to etch through the silicon wafer is completed at an initial through-etch time, and
the last of the one or more through-features to etch through the silicon wafer is completed at an etch completion time.

16. The method of claim 15 , wherein the patterned mask comprises silicon oxide.

17. The method of claim 15 , wherein before the top portion of the one or more nozzle through-holes and the outlet plenum are etched into the top surface of the silicon wafer, the bottom portion of the one or more nozzle through-holes and the cooling fluid outlet are filled with mounting oil.

18. The method of claim 15 , wherein the metallic coating comprises an aluminum coating.

19. The method of claim 18 , wherein coating the bottom comprises coating via an aluminum sputtering process.

20. The method of claim 15 , wherein the nozzle target depth and the plenum target depth are substantially equivalent depths through a thickness of the silicon wafer.

Assignees

• Toyota Eng & Mfg North America
• Univ Leland Stanford Junior

Inventors

• Zhou Feng
• Jung Ki Wook
• Dede Ercan Mehmet
• Asheghi Mehdi
• Goodson Kenneth E

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• H10W70/02

  of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10W40/47 Primary

  by flowing liquids, e.g. forced water cooling · CPC title