Adaptable can transceiver and system

Patent metadata

Field	Value
Publication number	US-10778481-B1
Application number	US-201916362785-A
Country	US
Kind code	B1
Filing date	Mar 25, 2019
Priority date	Mar 25, 2019
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A CAN transceiver includes a first terminal which receives a transmit signal from a CAN microcontroller. A splitter unit transmits a signal derived from the transmit signal to a CAN bus a via bus connection. A unit receives signals from the CAN bus via the bus connection. A second terminal sends a receive signal derived from the received signals to the CAN microcontroller. The transmit and receive signals include a pulsed signal waveform which represents data bits. Delay circuits apply a deliberate delay to the rising or falling edge of pulses of the transmit signal and/or a deliberate delay to the rising or falling edge of pulses of the receive signal.

First claim

I claim:

1. A controller area network (CAN) transceiver including:
a first terminal adapted to receive a transmit signal from a CAN microcontroller;
means to subsequently transmit signals derived from said transmit signal to a CAN bus via a bus connection;
means to receive signals from said CAN bus via said bus connection
a second terminal adapted to send a receive signal derived from said signals received from said CAN bus to said CAN microcontroller;
wherein said transmit and receive signals comprise a pulsed signal waveform, said pulsed signal waveform representing data bits; and
means which 1) applies a deliberate delay to a rising edge or to a falling edge of pulses of said transmit signal, thereby changing a width of said pulses of said transmit signal and 2) applies a second deliberate delay, consequent to said deliberate delay applied to said rising edge or to said falling edge of pulses of said transmit signal, to a rising edge or to a falling edge of said receive signal of pulses of said receive signal, thereby changing a width of said pulses of said receive signal.

2. The CAN transceiver as claimed in claim 1 where pulses of single bit duration transmitted to said CAN bus have a width of Tbit (bus) and said means which applies said first and second deliberate delays provides variation in said width.

3. The CAN transceiver as claimed in claim 1 wherein, said means which applies a deliberate delay comprises;
means to apply a deliberate delay to the rising edge of the pulses of said transmit signal and means to apply a corresponding deliberate delay to the rising edge of the receive signal consequent to the falling edge of the pulses of the receive signal.

4. The CAN transceiver as claimed in claim 1 , wherein said means which applies a deliberate delay comprises:
means to apply a delay to the falling edge of pulses of said transmit signal and means to apply a corresponding delay to the falling edge of receive signal consequent to the rising edge of the pulses of the receive signal.

5. The CAN transceiver as claimed in claim 1 , wherein said deliberate delays are trimmable.

6. The CAN transceiver as claimed in claim 1 where said pulses to which said deliberate delays are applied to said rising or falling edges are nominal recessive (REC) pulses in a CAN protocol system.

7. The CAN transceiver as claimed in claim 1 having means to logically combine CANH and CANL signals from the CAN bus form a signal for transmission to said second (CANRXD) terminal.

8. The CAN system comprising a plurality of CAN units, connected with each other via a common CAN bus; wherein each of the plurality of CAN units comprises a CAN microcontroller and a CAN transceiver as claimed in claim 1 , said CAN transceiver of each of said plurality of CAN units being connected to said common CAN bus.

Assignees

• Delphi Tech Ip Ltd

Inventors

• Glenn Jack L

Classifications

• H04B1/40 Primary

  Circuits · CPC title

• H04L2012/40215

  Controller Area Network CAN · CPC title

• H04L12/40006

  Architecture of a communication node (current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90) · CPC title

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• G06F13/36

  for access to common bus or bus system · CPC title