Clock dividing frequency circuit, control circuit and power management integrated circuit

Patent metadata

Field	Value
Publication number	US-10778231-B2
Application number	US-201715828610-A
Country	US
Kind code	B2
Filing date	Dec 1, 2017
Priority date	Dec 6, 2016
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A clock dividing frequency circuit can include: a controlled current source configured to generate a driving current that varies with a dividing frequency control signal; a ramp signal generating circuit configured to generate a ramp signal having a slope that varies according to the driving current, where the ramp signal is reset according to pulses of a dividing frequency clock signal; and a dividing frequency pulse generating circuit configured to generate the dividing frequency clock signal by a dividing frequency operation according to the ramp signal and a system clock signal.

First claim

What is claimed is:

1. A clock dividing frequency circuit, comprising:
a) a controlled current source configured to generate a driving current that varies with a dividing frequency control signal;
b) a ramp signal generating circuit configured to generate a ramp signal having a slope that varies according to said driving current, wherein said ramp signal is reset to a ground at zero volts according to pulses of a dividing frequency clock signal, wherein a frequency of said dividing frequency clock signal varies with said driving current; and
c) a dividing frequency pulse generating circuit configured to generate said dividing frequency clock signal by a dividing frequency operation according to said ramp signal and a system clock signal, wherein a frequency of said system clock signal is N times a frequency of said dividing frequency clock signal, and N is an integer that is greater than or equal to 2.

2. The clock dividing frequency circuit of claim 1 , wherein pulses of said system clock signal are configured as said dividing frequency clock signal when said ramp signal is higher than a predetermined threshold value.

3. The clock dividing frequency circuit of claim 1 , wherein said ramp signal generating circuit comprises:
a) a first capacitor configured to be charged by said driving current such that a voltage rise across said first capacitor rises to a reference voltage within a time interval that corresponds to said dividing frequency control signal; and
b) a first switch coupled in parallel with said first capacitor, wherein said first switch is controlled according to said dividing frequency clock signal.

4. The clock dividing frequency circuit of claim 3 , wherein:
a) said dividing frequency pulse generating circuit comprises a logic circuit configured to receive said ramp signal and said system clock signal, and to generate said dividing frequency clock signal; and
b) said reference voltage is configured as an input of said logic circuit.

5. The clock dividing frequency circuit of claim 3 , wherein said controlled current source comprises a transconductance amplifier configured to generate said driving current in accordance with said reference voltage and said dividing frequency control signal.

6. The clock dividing frequency circuit of claim 5 , wherein said dividing frequency control signal is configured as a compensation signal of a control loop circuit of a switching converter.

7. The clock dividing frequency circuit of claim 3 , wherein said dividing frequency pulse generating circuit comprises:
a) a comparator configured to compare said ramp signal against said reference voltage, and to generate an enable pulse signal; and
b) an AND logic circuit configured to generate said dividing frequency clock signal according to pulses of said system clock signal when a value of said enable pulse signal is at a predetermined level.

8. The clock dividing frequency circuit of claim 7 , wherein said controlled current source comprises:
a) a reference current generating circuit configured to generate a reference current control signal;
b) a first reference current source configured to generate a first reference current according to said reference current control signal, wherein said first reference current is configured to control said ramp signal generating circuit to generate said ramp signal having a predetermined slope; and
c) a current adjusting circuit coupled to said first reference current source, and being configured to adjust a current that flows to said ramp signal generation circuit according to said dividing frequency control signal.

9. The clock dividing frequency circuit of claim 8 , wherein said first reference current is configured to make said ramp signal increase to said reference voltage within N system clock cycles, and wherein N is greater than one.

10. The clock dividing frequency circuit of claim 8 , wherein said reference current generating circuit comprises:
a) a second reference current source configured to generate a second reference current according to said reference current control signal, wherein said ramp signal generating circuit is configured to generate said ramp signal in accordance with said second reference current; and
b) a control signal adjusting circuit configured to adjust said reference current control signal according to said ramp signal and said reference voltage such that said ramp signal has a predetermined slope.

11. The clock dividing frequency circuit of claim 10 , wherein said control signal adjusting circuit is configured to adjust said reference current control signal to make said ramp signal increase to said reference voltage in one clock cycle.

12. The clock dividing frequency circuit of claim 11 , wherein said control signal adjusting circuit is configured to adjust said reference current control signal according to said ramp signal and said reference voltage when said system clock cycle switches.

13. The clock dividing frequency circuit of claim 10 , wherein said ramp signal generating circuit comprises:
a) a second capacitor configured to be charged by said driving current; and
b) a second switch coupled in parallel with said second capacitor, wherein said second switch is configured to be controlled according to pulses of said system clock signal.

14. The clock dividing frequency circuit of claim 13 , wherein a capacitance value of said first capacitor is proportional to a capacitance value of said second capacitor.

15. The clock dividing frequency circuit of claim 10 , wherein said control signal adjusting circuit comprises:
a) a comparator configured to compare said ramp signal against said reference voltage, and to generate a state indication signal;
b) a D flip-flop configured to record said state indication signal when said system clock cycle switches, and to generate an adjustment indication signal; and
c) a current regulator configured to adjust said reference current control signal according to said adjustment indication signal.

16. The clock dividing frequency circuit of claim 8 , wherein said current adjustment circuit comprises:
a) a third reference current source configured to generate a third reference current proportional to said first reference current according to said reference current control signal;
b) a first diode coupled between said third reference current source and said first reference current source;
c) a transconductance amplifier configured to receive a dividing frequency reference voltage and said dividing frequency control signal; and
d) a second diode coupled between an output of said transconductance amplifier and an output of said third reference current source.

17. The clock dividing frequency circuit of claim 16 , wherein said dividing frequency control signal is configured as a feedback signal of a control loop circuit of a switching converter.

18. A control circuit, comprising the clock dividing frequency of claim 1 , wherein:
a) a compensation signal representing error information of an output signal of a switching converter is configured as said dividing frequency control signal to regulate said driving current of said controlled current source; and
b) said dividing frequency clock signal is configured to control an operation f a transistor of said switching converter.

19. A power management integrated circuit, comprising the clock dividing frequency circuit of claim 1 , and being configured to control a plurality of switching converters, wherein:
a) said clock dividing frequency circuit s configured to ge

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Tseng Jaime
• Chen Xiaoping
• Fan Hongfeng

Classifications

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H03K4/08

  having sawtooth shape · CPC title

• H03K21/08 Primary

  Output circuits · CPC title

• H03K23/40 Primary

  Gating or clocking signals applied to all stages, i.e. synchronous counters {(H03K23/74 - H03K23/84 take precedence)} · CPC title

• H03K3/037

  Bistable circuits · CPC title