Dynamic clock and voltage scaling with low-latency switching

Patent metadata

Field	Value
Publication number	US-9678556-B2
Application number	US-201414177073-A
Country	US
Kind code	B2
Filing date	Feb 10, 2014
Priority date	Feb 10, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a processor module configured to execute software instructions;
a plurality of clock divider modules, each of the clock divider modules configured to produce an output clock signal based on control inputs; and
a resource power manager module configured to receive a mode selection from the processor module, the mode selection indicating one of a plurality of operating modes comprising various frequency and voltage modes, the resource power manager module further configured to select one of a plurality of mode registers based on the mode selection, each one of the plurality of mode registers comprising both: (1) control inputs for operating the plurality of clock divider modules according to a respective one of the plurality of operating modes and to concurrently supply the control inputs from the selected one of the plurality of mode registers to control registers in at least two of the plurality of clock divider modules to operate according to the selected one of the plurality of operating modes; and (2) associated control inputs to signal a particular voltage level associated with the respective one of the plurality of operating modes, wherein each one of the plurality of mode registers comprises a clock divider value, a clock source selection value, and a clock output enable value, wherein the controller stabilizes the system clock and the silicon oscillator.

2. The integrated circuit of claim 1 , wherein operations of the plurality of clock divider modules controlled by the resource power manager module include selection of one of a plurality of input clock signals for each of the clock divider modules, and a divide value for each of the clock divider modules indicating a ratio between a frequency of the respective output clock signal and a frequency of the respective selected input clock signal.

3. The integrated circuit of claim 2 , wherein operations of the plurality of clock divider modules controlled by the resource power manager module further include selection of whether the output clock signal of each of the clock divider modules is enabled.

4. The integrated circuit of claim 2 , further comprising one or more phase-locked loops (PLLs), each of the PLLs configured to produce one or more clock signals,
wherein the resource power manager module is further configured to control the PLLs to operate according to the selected one of the plurality of operating modes, and
wherein the plurality of input clock signals of the plurality of clock divider modules includes the clock signals produced by the PLLs.

5. The integrated circuit of claim 1 , wherein controlling the plurality of clock divider modules to operate according to the selected one of the plurality of operating modes is an atomic operation.

6. The integrated circuit of claim 1 , wherein the resource power manager module is further configured to control a power management integrated circuit (PMIC) to supply a voltage supply to the integrated circuit according to the selected one of the plurality of operating modes based on the associated control inputs.

7. The integrated circuit of claim 6 , wherein the resource power manager module is further configured to control timing of controlling the PMIC relative to timing of controlling the plurality of clock divider modules.

8. The integrated circuit of claim 6 , wherein the plurality of operating modes includes two operating modes causing the PMIC to supply the voltage supply at the same level, each of the two operating modes causing at least one of the plurality of clock divider modules to produce the respective output clock signal at different frequencies.

9. A method for switching operating modes in an integrated circuit, the method comprising:
selecting one of a plurality of frequency-voltage modes as a new operating mode for the integrated circuit, each of the frequency-voltage modes specifying clock module controls and voltages for the integrated circuit;
signaling the voltages specified by the selected frequency-voltage mode to a power management integrated circuit;
selecting one of a plurality of mode registers based on the selected frequency-voltage mode, each one of the plurality of mode registers comprising the clock mode module controls specified by a respective one of the plurality of frequency-voltage modes; and
supplying the clock module controls from the selected one of the mode registers to a plurality of clock divider modules, each of the clock divider modules configured to produce an output clock signal based on the clock module controls;
wherein the clock module controls from the selected one of the mode registers are supplied to control registers in at least two of the plurality of clock divider modules concurrently and wherein each one of the plurality of mode registers further comprises a clock divider value, a clock source selection value, and a clock output enable value.

10. The method of claim 9 , wherein the clock module controls for each of the plurality of clock divider modules include a signal for selection of one of a plurality of input clock signals and a signal for a divide value indicating a ratio between a frequency of the respective output clock signal and a frequency of the respective selected input clock signal.

11. The method of claim 10 , wherein the clock module controls for each of the clock divider modules further include a signal for controlling whether the respective output clock is enabled.

12. The method of claim 10 , further comprising signaling phase-locked loop controls specified by the selected frequency-voltage mode to one or more phase-locked loops (PLLs), each of the PLLs configured to produce one or more clock signals based on the phase-locked loop controls, wherein the plurality of input clock signals of the plurality of clock divider modules includes the clock signals produced by the PLLs.

13. The method of claim 9 , wherein selecting one of the plurality of frequency-voltage modes is performed by a processor.

14. The method of claim 10 , wherein the plurality of frequency-voltage modes includes two frequency-voltage modes specifying a same voltage level, each of the two frequency-voltage modes specifying different clock module controls for at least one of the clock divider modules.

15. An integrated circuit, comprising:
a processor module configured to execute software instructions;
a plurality of clock divider modules, each of the clock divider modules configured to produce an output clock signal based on control inputs; and
a means for managing resource power configured to receive a mode selection from the processor module, the mode selection indicating one of a plurality of operating modes comprising various frequency and voltage modes, and configured to select one of a plurality of mode registers based on the mode selection, each one of the plurality of mode registers comprising both: (1) control inputs for operating the plurality of clock divider modules according to a respective one of the plurality of operating modes, and to concurrently supply the control inputs from the selected one of the mode registers to control registers in at least two of the plurality of clock divider modules to operate according to the selected one of the plurality of operating modes; and (2) associated control inputs to signal a particular voltage level associated with the respective one of the plurality of operating modes, wherein each one of the plurality of mode registers further comprises a clock divider value, a clock source selection value, and a clock output enable value.

16. The integrate

Assignees

• Qualcomm Inc

Inventors

• Pal Dipti Ranjan
• Penzes Paul Ivan
• Allam Mohamed Waleed

Classifications

• H03L7/22

  using more than one loop · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/3296

  by lowering the supply or operating voltage · CPC title