Phase change memory cell with constriction structure

Patent metadata

Field	Value
Publication number	US-10777739-B2
Application number	US-201715850632-A
Country	US
Kind code	B2
Filing date	Dec 21, 2017
Priority date	Mar 14, 2008
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

First claim

What is claimed is:

1. A method comprising:
forming a first electrode;
forming a second electrode; and
forming a memory element directly contacting the first and second electrodes, wherein forming the memory element includes forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element, the first portion of the memory element including a tapered part and a larger part, the larger part being larger than the tapered part and between the tapered part and the first electrode, wherein the programmable portion is formed to include a part of the tapered part of the first portion and a part of the second portion, the part of the first portion directly contacts the part of the second portion, and each of the part of the first portion and the part of the second portion is configured to change between multiple phases, wherein forming the memory element includes:
forming a first material over the first electrode;
removing a portion of the first material to form the larger part and the tapered part of the memory element, such that the larger part contacts the first electrode, the tapered part is over the larger part, and the larger part is between the tapered part and the first electrode;
forming a second material over the tapered part; and
removing a portion of the second material to form the second portion of the memory element.

2. A method comprising:
forming a first electrode;
forming a second electrode;
forming a memory element directly contacting the first and second electrodes, wherein forming the memory element includes forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element, and forming an intermediate material between the first and second portions, the intermediate material including a first material, and the first and second portions including a second material different from the first material, wherein forming the memory element includes:
depositing the second material over the first electrode;
forming a mask over the second material; and
using the mask to remove a part of the second material to obtain a remaining part of the second material, wherein the first portion include at least a part of the remaining part of the second material, and the intermediate material includes at least a part of the mask after the part of the second material is removed.

3. A method comprising:
forming a first electrode,
forming a second electrode; and
forming a memory element directly contacting the first and second electrodes, wherein forming the memory element includes forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element, the first portion of the memory element including a tapered part and a larger part, the larger part being larger than the tapered part and between the tapered part and the first electrode. wherein the programmable portion is formed to include a part of the tapered part of the first portion and a part of the second portion, the part of the first portion directly contacts the part of the second portion, and each of the part of the first portion and the part of the second portion is configured to change between multiple phases, wherein forming the memory element includes:
depositing a first material over the first electrode, wherein the first portion of the memory element includes at least a part of the first material;
forming an insulator over the first portion with an opening in the insulator to expose an exposed part of the first portion;
depositing a second material to fill the opening and cover the exposed part of the first portion; and
removing a part of the second material to obtain a remaining part of the second material and form the tapered part and the larger part. such that both the tapered and the larger part are inside the opening.

4. The method of claim 3 , wherein forming the second electrode includes depositing a third material over the second material before removing the part of the second material, and removing a part of the third material to obtain a remaining part of the third material, and wherein the second electrode includes at least a part of the remaining part of the third material.

5. A method comprising:
forming a first electrode;
forming a first material over the first electrode;
removing part of the first material to form a first portion of a memory element from a remaining part of the first material, such that the first portion includes a tapered part and a larger part, and the larger part is larger than the tapered part and between the tapered part and the first electrode;
forming a second material over the remaining part of the first material;
forming a third material over the second material; and
removing part of the second material and part of the third material after the second and third materials are formed in order to form a second portion of the memory element from a remaining part of the second material, and a second electrode from a remaining part of the third material, wherein a part of the second portion and a part of the tapered part of the first portion form a programmable portion of the memory element, and each of the part of the first portion and the part of the second portion is configured to change between multiple phases.

6. The method of claim 5 , wherein the first and second materials include a same material.

7. The method of claim 5 , wherein the first and second materials include a chalcogenide material.

8. The method of claim 5 , wherein the first material directly contacts the first electrode.

9. The method of claim 5 , wherein the remaining part of the first material has the tapered part.

10. The method of claim 9 , wherein the remaining part of the second material directly contacts the tapered part of the remaining part of the first material.

11. The method of claim 5 , wherein the third material directly contacts the second material.

12. The method of claim 11 , wherein the second and third materials include different materials.

13. A method comprising:
forming a first electrode;
forming a first chalcogenide material over the first electrode;
removing part of the first chalcogenide material to form a first portion of a memory element from a remaining part of the first chalcogenide material, the remaining part of the first chalcogenide material has a tapered part;
forming a second chalcogenide material over the tapered part of the remaining part of the first chalcogenide material;
forming a third material over the second chalcogenide material; and
removing part of the second chalcogenide material and part of the third material to form a second portion of the memory element from a remaining part of the second chalcogenide material, and a second electrode from a remaining part of the third material, wherein a part of the second portion and a part of the tapered part of the first the remaining part of the first chalcogenide material form a programmable portion of the memory element, and each of the part of the first portion and the part of the second portion is configured to change between multiple phases.

14. The method of claim 13 , wherein the second chalcogenide material directly contacts the tapered part of the remaining part of the first chalcogenide material.

15. The method of

Assignees

• Micron Technology Inc

Inventors

• Liu Jun
• Violette Michael P

Classifications

• H10N70/828 Primary

  Current flow limiting means within the switching material region, e.g. constrictions · CPC title

• H10N70/882

  Compounds of sulfur, selenium or tellurium, e.g. chalcogenides · CPC title

• H10N70/066

  by filling of openings, e.g. damascene method · CPC title

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10N70/884

  based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883) · CPC title