Planar and non-planar FET-based electrostatic discharge protection devices

Patent metadata

Field	Value
Publication number	US-10777546-B2
Application number	US-201615393723-A
Country	US
Kind code	B2
Filing date	Dec 29, 2016
Priority date	Nov 30, 2016
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) protection device, comprising:
a source region coupled to a first electrical node;
a first drain region coupled to a second electrical node different from the first electrical node; and
an extended drain region between the source region and the first drain region, the extended drain region comprising:
an N number of electrically floating doped regions, and
an M number of gate regions coupled to the second electrical node,
wherein N and M are integers greater than 1, and
wherein one or more electrically floating doped regions of the N number of electrically floating doped regions alternate with one or more gate regions of the M number of gate regions.

2. The ESD protection device of claim 1 , further comprising a well region having a first conductivity type, wherein the source region, the first drain region, and the N number of electrically floating doped regions are positioned within the well region and have a second conductivity type different from the first conductivity type.

3. The ESD protection device of claim 1 , further comprising:
a first well region having a first conductivity type;
a second well region having a second conductivity type different from the first conductivity type; and
wherein the source region, the first drain region, and the N number of electrically floating doped regions have the second conductivity type,
wherein the source region is positioned within the first well region, and
wherein the first drain region and an electrically floating doped region of the N number of electrically floating doped regions are positioned within the second well region.

4. The ESD protection device of claim 1 , further comprising:
a first well region having a first conductivity type; and
a second well region having a second conductivity type different from the first type of conductivity;
wherein the N number of electrically floating doped regions have the second conductivity type, and
wherein an electrically floating doped region of the N number of electrically floating doped regions is positioned partially within the first well region and partially within the second well region.

5. The ESD protection device of claim 1 , wherein the source region, the first drain region, and the N number of electrically floating doped regions comprise epitaxial fin regions.

6. The ESD protection device of claim 1 , further comprising a gate electrode, coupled to a first potential, between the source and extended drain regions.

7. The ESD protection device of claim 6 , further comprising a second drain region coupled to a second potential.

8. The ESD protection device of claim 7 , further comprising:
a well region on a substrate;
a second drain region coupled to the second potential;
a first discharging path comprising:
a first path from the first drain region to the well region, and
a second path from the well region to the source region; and

a second discharging path comprising:
a third path from the second drain region to the well region, and
a fourth path from the well region to the source region.

9. The ESD protection device of claim 6 , further comprising a parasitic transistor coupled to the source region and the first drain region.

10. The ESD protection device of claim 9 , further comprising:
a doped region, coupled to the first potential, having a conductivity type different from the source region and the first drain region; and
a parasitic resistor coupled to the parasitic transistor and the doped region.

11. The ESD protection device of claim 1 , wherein the first drain region comprises a K number of doped regions and an L number of gate regions coupled to the second electrical node, wherein K is an integer greater than 1, and L is an integer greater than or equal to 1.

12. The ESD protection device of claim 11 , wherein one or more electrically floating doped regions of the K number of doped regions alternate with one or more gate regions of the L number of gate regions.

13. The ESD protection device of claim 1 , further comprising:
a well region on a substrate; and
a discharging path comprising:
a first path from the first drain region to the well region; and
a second path from the well region to the source region.

14. The ESD protection device of claim 1 , further comprising:
an electrically floating gate region; and
an isolation region, wherein the source region is spaced apart from the isolation region by the electrically floating gate region.

15. An electrostatic discharge (ESD) protection device, comprising:
a first well region having a first conductivity type;
a second well region adjacent to the first well region and having a second conductivity type different from the first conductivity type;
a source region having the second conductivity type positioned within the first well region;
a first drain region having the second conductivity type and positioned within the second well region; and
an extended drain region having electrically floating doped regions and gate regions, wherein a first part of the extended drain region is positioned within the first well region.

16. The ESD protection device of claim 15 , wherein a second part of the extended drain region is positioned within the second well region.

17. The ESD protection device of claim 15 , wherein at least one of the electrically floating doped regions alternates with at least one of the gate regions of the extended drain region, and wherein the first drain region comprises more than one doped regions and at least one gate region.

18. The ESD protection device of claim 15 , further comprising:
a second drain region coupled to a same electrical node as the first drain region;
a first discharging path comprising:
a first path from the first drain region to the first well region, and
a second path from the first well region to the source region; and

a second discharging path comprising:
a third path from the second drain region to the first well region; and
a fourth path from the first well region to the source region.

19. An integrated circuit (IC), comprising:
an input/output (I/O) pad;
a power rail;
an electrostatic discharge (ESD) protection device coupled to the I/O pad and the power rail, the ESD protection device comprising:
a source region coupled to the power rail;
a drain region coupled to the I/O pad; and
an extended drain region between the source region and the drain region, the extended drain region comprising:
electrically floating doped regions, and
gate regions coupled to the I/O pad,
wherein each of the electrically floating doped regions alternates with each of the gate regions; and

an ESD protected circuit connected in parallel with the ESD protection device.

20. The IC of claim 19 , wherein the source region, the drain region, and
the electrically floating doped regions comprise epitaxial fin regions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Po-Lin
• Yang Han-Jen
• Lee Jam-Wem
• Chu Li-Wei

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D89/811 Primary

  using FETs as protective elements · CPC title

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title