Semiconductor device

Patent metadata

Field	Value
Publication number	US-10777545-B2
Application number	US-201916377563-A
Country	US
Kind code	B2
Filing date	Apr 8, 2019
Priority date	Nov 9, 2016
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A semiconductor device configures a protection element that protects a protection target element connected between a cathode electrode and an anode electrode when a parasitic transistor configured by a cathode region, a first conductivity type well layer, and a second conductivity type well is turned on and electrical continuity is established between the cathode electrode and the anode electrode. The semiconductor device includes a plurality of body regions in one cell of the protection element, and the plurality of body regions is brought in contact with the cathode electrode.

First claim

What is claimed is:

1. A semiconductor device configuring a protection element, comprising:
a semiconductor substrate having a first conductivity type well layer and a second conductivity type well layer being in contact with each other;
a cathode region disposed at a position away from a PN junction configured by the first conductivity type well layer and the second conductivity type well layer in a surface layer portion of the first conductivity type well layer, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second conductivity type well layer;
a plurality of body regions of a first conductivity type disposed at a plurality of positions different from the cathode region in the surface layer portion of the first conductivity type well layer;
an anode region disposed at a position away from the PN junction in a surface layer portion of the second conductivity type well layer, and having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second conductivity type well layer;
a gate insulating film disposed on a surface of a portion of the second conductivity type well layer located between the cathode region and the anode region;
a gate electrode disposed on the gate insulating film;
a cathode electrode electrically connected to the cathode region and electrically connected to the first conductivity type well layer through the plurality of body regions; and
an anode electrode electrically connected to the anode region, wherein
the protection element is configured to protect a protection target element connected between the cathode electrode and the anode electrode when a parasitic transistor configured by the cathode region, the first conductivity type well layer, and the second conductivity type well is turned on and electrical continuity is established between the cathode electrode and the anode electrode, and
the plurality of body regions is disposed in one cell of the protection element and is brought in Schottky contact with the cathode electrode.

2. The semiconductor device according to claim 1 , wherein
the first conductivity type well layer and the second conductivity type well layer have linear portions extending in one direction parallel to a surface of the semiconductor substrate, and a boundary line of the PN junction has a linear portion along the one direction,
the cathode region is one of a plurality of cathode regions,
the plurality of the cathode regions and the plurality of the body regions are aligned along the one direction, and
the anode region extends along the one direction.

3. The semiconductor device according to claim 1 , wherein
at least one of the first conductivity type well layer and the second conductivity type well layer is formed in a mesh pattern, and the other of the first conductivity type well layer and the second conductivity type well layer is formed at positions of meshes of the mesh pattern,
the cathode region is one of a plurality of cathode regions,
the anode region is one of a plurality of anode regions,
the plurality of the cathode regions and the plurality of the body regions are disposed in a lattice pattern at a position where the first conductivity type well layer is formed, and
the plurality of the anode regions is disposed in a lattice pattern at a position where the second conductivity type well layer is formed.

4. The semiconductor device according to claim 1 , wherein
the anode region has a circular shape,
the second conductivity type well layer has a circular shape disposed concentrically around the anode region,
the first conductivity type well layer is disposed concentrically with the anode region as a center,
the cathode region is one of a plurality of cathode regions, and
the plurality of the cathode regions and the plurality of the body regions are alternately disposed in a circular shape to surround the anode region.

5. A semiconductor device configuring a protection element, comprising:
a semiconductor substrate having a first conductivity type well layer and a second conductivity type well layer being in contact with each other;
a cathode region disposed at a position away from a PN junction configured by the first conductivity type well layer and the second conductivity type well layer in a surface layer portion of the first conductivity type well layer, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second conductivity type well layer;
a plurality of body regions of a first conductivity type disposed at a plurality of positions different from the cathode region in the surface layer portion of the first conductivity type well layer;
an anode region disposed at a position away from the PN junction in the surface layer portion of the second conductivity type well layer and having the second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second conductivity type well layer;
a gate insulating film disposed on a surface of a portion of the second conductivity type well layer located between the cathode region and the anode region;
a gate electrode disposed on the gate insulating film;
a cathode electrode electrically connected to the cathode region and electrically connected to the first conductivity type well layer through the plurality of body regions; and
an anode electrode electrically connected to the anode region, wherein
the protection element is configured to protect a protection target element connected between the cathode electrode and the anode electrode when a parasitic transistor configured by the cathode region, the first conductivity type well layer, and the second conductivity type well is turned on, and electrical continuity is established between the cathode electrode and the anode electrode,
the plurality of body regions is disposed in one cell of the protection element, and each of the plurality of the body regions includes a high resistance layer of the first conductivity type, and
the high resistance layer is disposed at a position above the first conductivity type well layer, is higher in resistance than the first conductivity type well layer, and is brought in contact with the cathode electrode.

6. The semiconductor device according to claim 5 , wherein
the high resistance layer is a high resistance polysilicon layer or a high resistance silicide layer.

7. The semiconductor device according to claim 5 , wherein
the first conductivity type well layer and the second conductivity type well layer have linear portions extending in one direction parallel to a surface of the semiconductor substrate, and a boundary line of the PN junction has a linear portion along the one direction,
the cathode region is one of a plurality of cathode regions,
the plurality of the cathode regions and the plurality of the body regions are aligned along the one direction, and
the anode region extends along the one direction.

8. The semiconductor device according to claim 5 , wherein
at least one of the first conductivity type well layer and the second conductivity type well layer is formed in a mesh pattern, and the other of the first conductivity type well layer and the second conductivity type well layer is formed at positions of meshes of the mesh pattern,
the cathode region is one of a plurality of cathode regions,
the anode region is one of a plurality of anode regions,
the plurality of the cathode regions and the plurality of the body regions are disposed in a lattice pattern at a position where the first conductivity type well layer is formed,

Assignees

• Denso Corp

Inventors

• Yamada Akira
• Sakurai Shinya
• Nakano Takashi
• Kondo Yosuke
• Motojima Mutsuya

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D89/815 Primary

  involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor · CPC title

• H10D84/153

  the built-in component being PN junction diodes · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title