Reliable passivation for integrated circuits

Patent metadata

Field	Value
Publication number	US-10777519-B2
Application number	US-201916448457-A
Country	US
Kind code	B2
Filing date	Jun 21, 2019
Priority date	Feb 12, 2016
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

First claim

What is claimed is:

1. A device comprising:
a substrate including a back-end-of-line (BEOL) dielectric layer and an interconnect in the BEOL dielectric layer;
a pad dielectric layer disposed over the BEOL dielectric layer, the pad dielectric layer including a pad via opening which exposes a surface of the interconnect in the BEOL dielectric layer;
a pad interconnect disposed on the pad dielectric layer, the pad interconnect including a pad interconnect structure and a pad via contact in the pad via opening, the pad interconnect structure having a pad interconnect pattern which is devoid of 90° angles due to corner rounding provided by optical proximity correction; and
a composite passivation layer including a first dielectric liner and a second dielectric liner on the first dielectric liner, the first dielectric liner conformally lining the pad dielectric layer and the pad interconnect structure, and the second dielectric liner conformally lining the first dielectric liner,
wherein the first dielectric liner is comprised of silicon oxide and has a thickness of about 4,000 Å to about 6,000 Å, the second dielectric liner is comprised of silicon nitride and has a thickness of about 4,000 Å to 6,000 Å, and the pad interconnect structure has a T-shape or a U-shape that includes corner rounding with a plurality of bends that are chamfered to 45°.

2. The device of claim 1 wherein the pad interconnect structure has a thickness greater than about 20,000 Å.

3. The device of claim 1 wherein the second dielectric liner is disposed completely and directly on the first dielectric liner.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Lee Fook Hong
• Tan Juan Boon
• KHOR Ee Jan

Classifications

• H10W72/5525

  comprising copper [Cu] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title