Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10777490-B2
Application number	US-201916684897-A
Country	US
Kind code	B2
Filing date	Nov 15, 2019
Priority date	Apr 27, 2017
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip having:
an electrode pad including a first bonding surface; and
an insulating film including a first opening that exposes the first bonding surface of the electrode pad;

a first wire bonded to the first bonding surface of the electrode pad; and
a sealer sealing the semiconductor chip and the first wire such that the sealer is in contact with the first bonding surface of the electrode pad,
wherein the first bonding surface is made of metal,
wherein the sealer is made of an insulating material,
wherein, in plan view, the first bonding surface includes:
a first region;
a second region; and
a third region between the first region and the second region,

wherein the first wire includes:
a first bonding portion bonded to the first region of the first bonding surface;
a second bonding portion bonded to the second region of the first bonding surface; and
a first middle portion located between the first bonding portion and the second bonding portion, and spaced apart from the third region of the first bonding surface, and

wherein, in plan view, each of a width of the first region and a width of the second region is larger than a width of the third region, each width being a length in a second direction crossing to the first direction.

2. The semiconductor device according to claim 1 ,
wherein the first opening includes:
a first side formed on one end of the first opening in the second direction and extending in the first direction; and
a second side formed on an end opposite to the first side and extending in the first direction,

wherein the first side bends at each of a part between the first region and the third region and a part between the second region and the third region, and
wherein the second side bends at each of a part between the first region and the third region and a part between the second region and the third region.

3. The semiconductor device according to claim 1 ,
wherein, in plan view, the width of the third region is equal to or smaller than a width of the first middle portion of the first wire.

4. The semiconductor device according to claim 1 ,
wherein, in the second direction, a second wire is arranged adjacent to the first wire, and
wherein a separation distance between the first wire and the second wire in the second direction is smaller than a wire diameter of the first wire.

5. The semiconductor device according to claim 1 ,
wherein, in plan view, the first opening includes:
a first side extending in the first direction; and
a second side opposite to the first side,

wherein, in plan view, the first side includes:
a first portion extending along the first region;
a second portion extending along the second region; and
a third portion located between the first portion and the second portion and extending along the third region, and

wherein a width between an extension line of the first portion of the first side and the third portion is larger than a width between the third portion of the first side and the first middle portion of the first wire.

6. The semiconductor device according to claim 1 ,
wherein, in plan view, the first opening includes:
a first side extending in the first direction; and
a second side opposite to the first side,

wherein, in plan view, the first side includes:
a first portion extending along the first region;
a second portion extending along the second region; and
a third portion located between the first portion and the second portion and extending along the third region,

wherein, in plan view, the second side includes:
a fourth portion extending along the first region;
a fifth portion extending along the second region; and
a sixth portion located between the fourth portion and the fifth portion and extending along the third region,

wherein the third portion of the first side is located between an extension line of the first portion and the second side, and
wherein the sixth portion of the second side is located between an extension line of the fourth portion and the first side.

7. The semiconductor device according to claim 1 ,
wherein the first region of the first bonding surface has a first protruding portion protruding in the second direction, and,
wherein, in plan view, a length of the first protruding portion in the first direction is shorter than a length of the first region in the first direction.

8. The semiconductor device according to claim 7 ,
wherein, in plan view, a length of the first protruding portion in the second direction is shorter than a length of the first protruding portion in the first direction.

9. The semiconductor device according to claim 1 ,
wherein, in plan view, the first opening includes:
a first side extending in the first direction; and
a second side opposite to the first side,

wherein the first region of the first bonding surface includes:
a first protruding portion protruding in the second direction from the first side of the first opening; and
a second protruding portion protruding in the second direction from the second side of the first opening, and

wherein, in a plan view, each of a length of the first protruding portion in the first direction and a length of the second protruding portion in the first direction is shorter than a length of the first region in the first direction.

10. The semiconductor device according to claim 9 ,
wherein, in plan view, the second region of the first bonding surface includes:
a third protruding portion protruding in the second direction from the first side of the first opening; and
a fourth protruding portion protruding in the second direction from the second side of the first opening, and

wherein, in a plan view, each of a length of the third protruding portion in the first direction and a length of the fourth protruding portion in the first direction is shorter than a length of the second region in the first direction.

11. The semiconductor device according to claim 1 ,
wherein the third region of the first bonding surface has a first hollow portion hollowing in the second direction toward the third region, and
wherein, in plan view, a length of the first hollow portion in the first direction is shorter than a length of the third region in the first direction.

12. The semiconductor device according to claim 1 ,
wherein, in plan view, the first opening includes:
a first side extending in the first direction; and
a second side opposite to the first side,

the third region of the first bonding surface includes:
a first hollow portion hollowing in the second direction from the first side of the first opening toward the second side; and
a second hollow portion hollowing in the second direction from the second side of the first opening toward the second side, and

wherein, in plan view, each of a length of the first hollow portion in the first direction and a length of the second hollow portion in the first direction is shorter than a length of the third region in the first direction.

13. The semiconductor device according to claim 1 ,
wherein the third region has a mark formed by intrusion of a test terminal.

14. A semiconductor device comprising:
a semiconductor chip having:
an electrode pad including a first bonding surface; and
an insulating film including a first opening that exposes the first bonding surface of the electrode pad;

a first wire bonded to the first bonding surface of the electrode pad; and
a sealer sealing the semiconductor chip and the first wire such that the sealer is in contact with the fi

Assignees

• Renesas Electronics Corp

Inventors

• Sato Yukihiro
• Kiyohara Toshinori

Classifications

• H10W72/642

  being orthogonal to a side surface of the chip, e.g. in parallel arrangements · CPC title

• H10W72/07652

  changes in structures or sizes · CPC title

• H10W72/627

  Multiple strap connectors having different structures or shapes · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title