Save-restore circuitry with metal-ferroelectric-metal devices

Patent metadata

Field	Value
Publication number	US-10777250-B2
Application number	US-201816144896-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A circuit comprising:
a first inverter and a second inverter cross-coupled between a bit node and a bit bar node;
a save-restore circuit coupled to the bit node, the save-restore circuit including:
a metal-ferroelectric-metal (MFM) device to store a logic value of the bit node when the circuit is in a sleep state and restore the logic value to the bit node when the circuit transitions from the sleep state to an active state, wherein the MFM device is coupled between an internal node and a plate line, wherein the plate line is to receive a control signal to control the MFM device to perform the store and the restore;
a transmission gate coupled between the MFM device and the bit node to isolate the MFM device from the bit node when the circuit is in the active state; and
a selector device coupled between the internal node and ground to initialize the internal node prior to the store and prior to the restore.

2. The circuit of claim 1 , wherein the save-restore circuit further comprises a capacitive load coupled between the internal node and ground.

3. The circuit of claim 1 , wherein the capacitive load is another MFM device.

4. The circuit of claim 1 , wherein the first inverter and second inverter are responsive to respective control signals to be tri-stated as part of the restore of the logic value to the bit node.

5. The circuit of claim 1 , wherein the save-restore circuit is a first save-restore circuit, wherein the MFM device is a first MFM device, and wherein the circuit further includes a second save-restore circuit coupled to the bit bar node, the second save-restore circuit including a second MFM device to store a logic value of the bit bar node when a flip-flop circuit is in a sleep state and restore the logic value to the bit bar node when the flip-flop circuit transitions from the sleep state to an active state.

6. The circuit of claim 5 , wherein, during a first store operation, one of the first MFM device or the second MFM device is to store the logic value of the respective bit node or bit bar node based on a state of the bit node and bit bar node, and, during a second store operation that occurs before or after the first store operation, the other one of the first MFM device or the second MFM device is to store the logic value of the respective bit node or bit bar node based on the state of the bit node and bit bar node.

7. The circuit of claim 1 , wherein the circuit is included in a flip-flop circuit.

8. The circuit of claim 1 , wherein the circuit is included in a register file circuit.

9. A flip-flop circuit comprising:
a first inverter and a second inverter cross-coupled between a bit node and a bit bar node;
a first metal-ferroelectric-metal (MFM) device coupled between an internal node and a plate line, wherein the first MFM device is to store a logic value of the bit node when the flip-flop circuit is in a sleep state and restore the logic value to the bit node when the flip-flop circuit transitions from the sleep state to an active state, and wherein the plate line is to receive a control signal to control the first MFM device to perform the store and the restore;
a second MFM device coupled between the internal node and ground to provide charge-sharing with the first MFM device for the restore;
a transmission gate coupled between the internal node and the bit node to isolate the first and second MFM devices from the bit node when the flip-flop circuit is in the active state; and
a selector device coupled between the internal node and ground to initialize the internal node prior to the store and prior to the restore.

10. The flip-flop circuit of claim 9 , wherein the first inverter and second inverter are responsive to respective control signals to be tri-stated as part of the restore of the logic value to the bit node.

11. The flip-flop circuit of claim 9 , wherein the first and second MFM devices and the transmission gate are included in a first save-restore circuit coupled to the bit node, and wherein the flip-flop circuit further includes a second save-restore circuit coupled to the bit bar node.

12. A register file circuit comprising:
a bitcell having a bit node and a bit bar node;
a first metal-ferroelectric-metal (MFM) device coupled between an internal node and a plate line, the first MFM device to store a logic value of the bit node when a flip-flop circuit is in a sleep state and restore the logic value to the bit node when the flip-flop circuit transitions from the sleep state to an active state;
a second MFM device coupled between the internal node and ground to provide charge-sharing with the first MFM device for the restore; and
a transmission gate coupled between the internal node and the bit node to isolate the first and second MFM devices from the bit node when the flip-flop circuit is in the active state; and
a selector device coupled between the internal node and ground to initialize the internal node prior to the store and prior to the restore.

13. The register file circuit of claim 12 , wherein the plate line is to receive a control signal to control the first MFM device to perform the store and the restore.

14. The register file circuit of claim 12 , wherein the first MFM device, the second MFM device, and the transmission gate are included in a first save-restore circuit coupled to the bit node, and wherein the flip-flop circuit further includes a second save-restore circuit coupled to the bit bar node, the second save-restore circuit including a third MFM device and a fourth MFM device.

15. The register file circuit of claim 14 , wherein, during a first store operation, one of the first MFM device or the third MFM device is to store the logic value of the respective bit node or bit bar node based on a state of the bit node and bit bar node, and, during a second store operation that occurs before or after the first store operation, the other one of the first MFM device or the third MFM device is to store the logic value of the respective bit node or bit bar node based on the state of the bit node and bit bar node.

16. The register file circuit of claim 12 , wherein the restore is performed using a global power rail of the register file circuit that is at an active mode voltage during the active state and at a sleep mode voltage during the sleep state.

17. A computer system comprising:
a battery;
one or more antennas; and
a processor coupled to the battery and the one or more antennas, the processor including:
a logic circuit;
a power management circuit to switch the logic circuit between an active state and a sleep state;
a circuit coupled to the logic circuit to store data for the logic circuit while the logic circuit is in the sleep state and restore the data when the logic circuit transitions from the sleep state to the active state, wherein the circuit includes:
a first inverter and a second inverter cross-coupled between a bit node and a bit bar node;
a first metal-ferroelectric-metal (MFM) device coupled between an internal node and a plate line, the first MFM device to store a logic value of the bit node when the logic circuit is in the sleep state and restore the logic value to the bit node when the logic circuit transitions from the sleep state to the active state;
a second MFM device coupled between the internal node and ground; and
a transmission gate coupled between the internal node and the bit node to isolate the MFM device from the bit node when the logic circuit is in the active state; and
a selector device coupled between the internal node and ground to initialize the

Assignees

• Intel Corp

Inventors

• Vaidyanathan Kaushik
• Morris Daniel H
• Liu Huichu
• Kurian Dileep J
• Avci Uygar E
• Karnik Tanay
• Young Ian A

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/2275 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C14/0072 Primary

  and the nonvolatile element is a ferroelectric element · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title